Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
264
Note: Base Address for the Watchdog Timer registers, listed in this section, is configurable.
11.10.3.1 Offset 00h: PV1R0 - Preload Value 1 Register 0
Table 387. Watchdog Timer Register Summary: IA F Base (IO) View
Offset
Start
Offset End Register ID - Description Default
Value
00h 00h “Offset 00h: PV1R0 - Preload Value 1 Register 0” on page 264 FFh
01h 01h “Offset 01h: PV1R1 - Preload Value 1 Register 1” on page 265 FFh
02h 02h “Offset 02h: PV1R2 - Preload Value 1 Register 2” on page 265 0Fh
04h 04h “Offset 04h: PV2R0 - Preload Value 2 Register 0” on page 266 FFh
05h 05h “Offset 05h: PV2R1 - Preload Value 2 Register 1” on page 266 FFh
06h 06h “Offset 06h: PV2R2 - Preload Value 2 Register 2” on page 266 0Fh
0Ch 0Ch “Offset 0Ch: RR0 - Reload Register 0” on page 267 00h
0Dh 0Dh “Offset 0Dh: RR1 - Reload Register 1” on page 267 00h
10h 10h “Offset 10h: WDTCR - WDT Configuration Register” on page 268 00h
14h 14h “Offset 14h: DCR0 - Down Counter Register 0” on page 268 00h
15h 15h “Offset 15h: DCR1 - Down Counter Register 1” on page 269 00h
16h 16h “Offset 16h: DCR2 - Down Counter Register 2” on page 269 00h
18h 18h “Offset 18h: WDTLR - WDT Lock Register” on page 269 00h
Table 388. 00h: PV1R0 - Preload Value 1 Register 0
Size: 8 bit Default: FFh Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
00h
00h
IA F Base Address: Base (IO) Offset: 00h
Bit Range Default Access Acronym Description
07 : 00 FFh RW PLOAD1_7_0
Preload_Value_1 [7:0]: This register is used to hold the bits 0 through
7 of the preload value 1 for the WDT Timer. The Value in the Preload
Register is automatically transferred into the 35-bit down counter.
The value loaded into the preload register needs to be one less than the
intended period. This is because the timer makes use of zero-based
counting (i.e. zero is counted as part of the decrement).
Refer to Section 11.10.4.2 for details on how to change the value of this
register.