Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
262
The following table shows the different device write times for doing a 512 kB sector
write.
11.9.7.3 SPI Initialization
This section provides a high level description of the steps that the BIOS should take
upon coming out of RESET when using SPI Flash.
1. Boot vector fetch and other initial BIOS reads using Direct Memory Reads (some of
which are 64 byte code reads). Caching is enabled in hardware by default to
improve performance on consecutive reads to the same line.
2. Turn on the SPI Prefetching policy in the LPC Bridge Configuration Space (Offset
D8h: BC: BIOS Control Register). This policy bit is in configuration space to avoid
requiring protected memory space early in the boot process.
3. Copy the various BIOS modules out of the SPI Flash using Direct Memory Reads. It
is assumed that these reads are shorter than 64 bytes and are targeted to
consecutive addresses; hence, the prefetch mechanism improves the performance
of this sequence.
4. Turn off the SPI Prefetch policy.
5. Program opcode registers in order to discover which Flash device is being used.
Four of the six supported Flash devices support the READ ID instruction. Details of
the discovery algorithm are outside the scope of this specification.
6. Disable Future Request, Offset 02h: SPIC – SPI Control bit 0. Default state is
Future Request enabled.
7. Re-program opcode registers to support specific Flash vendor’s commands. If not
using all of the Opcode Menu and Prefix Opcodes, BIOS should program a “safe”
value in the unused opcodes to minimize what malicious software can do. A
suggested safe value is to replicate one of the valid entries.
a. Offset 54h: PREOP – Prefix Opcode Configuration
b. Offset 56h: OPTYPE – Opcode Type Configuration
c. Offset 58h: OPMENU – Opcode Menu Configuration
8. Setup protection registers as needed.
a. Offset 50h: BBAR – BIOS Base Address
b. Offset 60h: PBR0 – Protected BIOS Range [0-2]
c. Offset 64h: PBR1 – Protected BIOS Range #1
d. Offset 68h: PBR2 – Protected BIOS Range #2
Table 386. Flash Write Time
Device Write Time
Worst Case/
Typical
Description
PMC* PM25LV 41/8 s
Atmel* AT25F 1/.7 s
SST* SST25VF ~13 s
Two options for byte writes with this device: byte write and byte write
with auto address increment. However, only the standard byte write is
supported by the processor. The Worst Case time accounts for re-
transmission of Write Enable, Write with Address, Read Status, and
platform inter- command delay (total of ~5 us).
NexFlash* NX25P 41/16 s
ST* M25P80 4/11.71 s
ST* M45P80 41/10 s