Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
260
Note that once BIOS has locked down the BIOS BAR, this mechanism remains in place
until the next system reset.
There is one exception where processor-initiated reads may access data below the
BIOS Base Address. If a programmed read (or Direct Memory Read) is initiated at the
top of flash such that the length exceeds the top of flash memory, the read burst may
wrap around to location 0.
11.9.5.14.4 Decoding Memory Range for SPI
The Boot BIOS Destination straps are sampled on the rising edge of PWROK. The
Feature space ranges are unique to the FWH flash. However, the feature space can be
treated just like standard memory from an SPI perspective and therefore allow up to 16
MB of contiguous memory decode. The processor forwards both data and feature space
ranges to the SPI interface (although the BIOS BAR may block the feature space
accesses in situations where the flash size is less than 4 MB). Of course, in order to
utilize 16 MB, the single flash device would need to support 128 Mbits of data.
The Top Swap mechanism works in the same way that it does on LPC. Address bit 16 is
inverted when Top Swap is enabled for any accesses to the upper two 64 kB blocks.
Also like LPC, the Top Swap functionality does not apply to accesses generated to the
holes below 1 MB. The SPI interface performs the address bit inversion on only the
Direct Memory Read access method; software can control the address directly with the
programmed command access method. The prefetching and caching logic consistently
comprehends the address inversion to avoid delivering bad data. Also, the protection
mechanisms described above observe the address after the inversion logic.
Memory writes to the BIOS memory range are dropped. This simplifies the hardware
architecture, and forces all of these potentially harmful cycles to go through the
Programmed Commands interface.
Note that Direct Memory Reads to the E0000h-FFFFFh segments are remapped to top
of flash as mentioned previously in Section 11.9.5.12.1. This range is not remapped
when using Programmed Accesses.
11.9.6 SPI Clocking
The SPI clock, when driven by the processor, is derived from the 100 MHz “backbone”
clock. The SPI Clock Selection fuse defaults to dividing the 100 MHz clock by 5,
resulting in a clock frequency of 20 MHz (50 ns clock period).
Implementation Note: The duty cycle is 40% and 60%.
Note that a DFT divide-by-5 mode is added for determinism with the clock sets planned
for the tester.
11.9.7 BIOS Programming Considerations
In general, any Flash update can be broken down into two steps.
1. Erase
2. Write
The Erase process initializes the addressed sector to FFh, erase times for the supported
Flash devices are shown below. The atomic instructions that make up the Erase process
are a Write enable instruction, an Erase instruction, and finally a status poll.