Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
258
11.9.5.13 Generic Programmed Commands
All commands other than the standard (memory) reads must be programmed by the
BIOS in the SPI Control, address, data, and opcode configuration registers in
Section 11.9.5.1. The opcode type in Offset 56h: OPTYPE – Opcode Type Configuration
and data byte count fields in Offset 54h: PREOP – Prefix Opcode Configuration
determine how many clocks to run before deasserting the chip enable. The flash data is
always shifted in for the number of bytes specified and the BIOS out data is always
shifted out for the number of data bytes specified.
Note that the hardware restricts the burst lengths that are allowed.
The status bit in Offset 00h: SPIS – SPI Status indicates when the cycle has completed
on the SPI port allowing the host to know when read results can be checked and/or
when to initiate a new command.
The processor also provides the “Atomic Cycle Sequence” for performing erases and
writes to the SPI flash in Offset 02h: SPIC – SPI Control. When this bit is 1 (and the SPI
Cycle Go bit is written to 1), a sequence of cycles is performed on the SPI interface. In
this case, the specified cycle is preceded by the Prefix Command (8-bit programmable
opcode) and followed by repeated reads to the Status Register (opcode 05h) until bit 0
indicates the cycle has completed. The hardware does not attempt to check that the
programmed cycle is a write or erase.
If a Programmed Access is initiated (SPI Cycle Go written to 1) while the SPI host
interface logic is already busy with a Direct Memory Read, then the SPI Host hardware
will hold the new Programmed Access pending until the preceding SPI access
completes. It will then begin to request the SPI bus for the Programmed Access.
Once the SPI Host hardware has committed to running a programmed access,
subsequent writes to the programmed cycle registers that occur before it has
completed will not modify the original transaction and will result in the assertion of the
Blocked Access Status bit in Offset 00h: SPIS – SPI Status. Software should never
purposely behave in this way and rely on this behavior. However, the Blocked Access
Status bit provides basic error-reporting in this situation. Writes to the following
registers causes the Blocked Access Status bit assertion in this situation:
Offset 02h: SPIC – SPI Control
Offset 04h: SPIA – SPI Address
Offset 08h: SPID0 – SPI Data 0
11.9.5.14 Flash Protection
There are two types of Flash Protection mechanisms:
1. BIOS Range Write Protection
2. SMI# - Based Global Write Protection
The two mechanisms are conceptually ORed together such that if any of the
mechanisms indicate that the access should be blocked, then it is blocked. Table 384
provides a summary of the two mechanisms.