Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
257
Note that, although the SPI interface may “burst ahead” for up to 64 bytes, the Host
Interface may still have to wait for prefetched data to arrive from the flash before
generating the completion back to the processor. The round trip delay for the platform
to complete one DWord and run the host read for the next sequential DWord can be
shorter than the SPI time to receive another 32 bits.
If a Direct Memory Read targeting the SPI flash is received while the host interface is
already busy with either another Direct Memory Read or a Programmed Access, then
the SPI Host hardware will hold the new Direct Memory Read (and the host processor)
pending until the preceding SPI access completes. Note that it is possible for a second
Direct Memory Read to be received while the prefetching continues for a first Direct
Memory Read.
The SPI interface provides empty flash detection equivalent to FWH (i.e., 1’s on the
initial boot access.)
It is possible that a Direct Memory Read targeting the SPI flash can be issued with
noncontiguous byte enables. While the CPU cannot create these cycles, peer agents
can.
The SPI interface handles these Direct Memory Read transactions in the following
fashion. Note that the byte enables in the table are active high, and BE[3] is the most
significant byte enable of the DWord.
When coming out of a platform reset, the SPI Host Controller must hold the initial
Direct Memory Read from the processor pending until the SPI flash is no longer busy
with an internal write or erase instruction. In order to achieve this, the host controller
reads the Status Register (opcode = 05h) of the flash device until bit 0 is cleared. This
is equivalent to the polling performed following an atomic cycle, during which the Direct
Memory Reads are held pending. Depending on the type of flash and type of long
instruction performed, the delay could be long enough to cause a watchdog time-out in
the processor or chipset. Although this error condition is deemed acceptable in
response to this rare error scenario (reset during flash update), it can be avoided
altogether by selecting flash instructions on SPI devices that complete in less than ~1
second. Note that in the typical boot case, the status read on the SPI interface will
complete well before the processor boot fetch due to the delay from reset deassertion
to CPURST# deassertion.
Table 383. Byte Enable Handling on Direct Memory Reads
# DWords
Requested
First DWord BE[3:0] Last DWord
BE[3:0]
Action Taken
1 0000 Don’t Care
Zero bytes read from SPI, no SPI
transaction started
1
0001, 0010, 0100, 1000, 0011, 0110, 1100,
0111, 1110, 1111
Don’t Care
Bytes read from SPI = bytes
requested starting from lowest
requested byte
1 0101, 1001, 1010, 1011, 1101 Don’t Care
Full DW (4 bytes) requested from
SPI
>1 0000 Don’t Care Undefined behavior. Illegal protocol
>1 1000, 1100, 1110, 1111 Don’t Care
Bytes read from SPI = 4* (num DW
- 1) + bytes requested in first DW.
Address starts from lowest
requested byte.
>1
0001, 0010, 0011, 0100, 0101,
0110, 0111, 1001, 1010, 1011,
1101
Don’t Care Bytes read from SPI = 4* num DW