Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
256
11.9.5.12 Running SPI Cycles from the Host
11.9.5.12.1 Memory Reads
Memory Reads to the BIOS Range result in a READ command (03h) with the lower 3
bytes of the address delivered in the SPI cycle. By sending the entire 24 bits of address
out to the SPI interface unchanged, the processor hardware can support various flash
memory sizes without having straps or automatic detection algorithms in hardware.
The flash memory device must ignore the upper address bits such that an address of
FFFFFFh simply aliases to the top of the flash memory. This is true for all supported
flash devices. When considering additional flash parts, this behavior should be checked.
For compatibility with the FWH interface, the SPI interface supports decoding the two
64 KB BIOS ranges at the E0000h and F0000h segments just below 1 MB. These ranges
must be re-directed (aliased) to the ranges just below 4 GB by the processor. This is
done by forcing the upper address bits (23:20) to 1’s when performing the read on the
SPI interface.
When the SPI Prefetch Enable bit in Offset D8h: BC: BIOS Control Register is set, the
processor checks if the starting address for a read is aligned to the start of a 64B block
(i.e., address bits 5:0 are 00h). If this is not the case, then the processor only reads
the length specified by the current read. If the read is aligned to the start of the 64B
block with the SPI Prefetch Enable bit set, then the read burst continues on the SPI pins
until 64 bytes have been received. Note that the processor always performs the entire
64B burst when the conditions are met to perform the prefetch when the memory read
request is received. This policy can result in a large penalty if the read addresses are
not sequential. Software is allowed and encouraged to dynamically turn on prefetching
only when the reads are sequential (for example, if shadowing the BIOS using
consecutive DWord reads).
When prefetching is enabled, the read buffer must be enabled for caching. If the
processor detects a read to the range that is currently in (or being fetched for) the read
buffer, it will not perform another read cycle on the SPI pins. Instead, the data is
returned from the read buffer. Note that the entire read request must be contained in
the cache in order to avoid running the read on the SPI interface.
The following events invalidate the read buffer “cache”:
1. A Programmed Access begins. Note that if the cycle is blocked from running for
protection or other reasons, the cache is not flushed.
2. A Memory read to a BIOS range that does not hit the range in the read buffer
3. System Reset
4. Software setting the Cache Disable bit (and clearing the Prefetch Enable) in Offset
D8h: BC: BIOS Control Register. This can serve as a way to flush the cache in
software.
Even when prefetching is disabled, the read buffer can act as a cache for Direct
Memory Read Data. This is a potentially valuable boot-time optimization that leverages
the basic caching mechanism that is needed for prefetching anyway. The cache is
loaded with the data received on every Direct Memory Read that runs on the SPI pins.
That data remains valid within the cache until any one of the conditions listed above
occurs. For the cache to work properly, the Direct Memory Read must be fully contained
within a 64-byte aligned range. The following events result in a valid read buffer cache
when the caching is enabled:
1. A host read to the SPI BIOS with a length of 64 Bytes. This cycle must be aligned to
a 64B boundary.
2. A host read to the SPI BIOS of any length with a 64B-aligned address and
prefetching is enabled.