Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
255
It is recommended that BIOS avoid programming Write Enable opcodes in this menu.
Malicious software could then perform writes and erases to the SPI flash without using
the atomic cycle mechanism. Write Enable opcodes should only be programmed in the
Offset 54h: PREOP – Prefix Opcode Configuration.
11.9.5.11 Offset 60h: PBR0 – Protected BIOS Range [0-2]
This register can not be written when the SPI Configuration Lock-Down bit in Offset
00h: SPIS – SPI Status register is set to 1.
Table 381. 58h: OPMENU - OPCODE Menu Configuration
Size: 64 bit Default: 00000005h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
3078h
307Fh
Memory Mapped IO BAR: RCBA Offset:
Bit Range Default Access Acronym Description
63 :56 0 RWS AO7 Allowable Opcode 7: See the description for bits 7:0
55 :48 0 RWS AO6 Allowable Opcode 6: See the description for bits 7:0
47 :40 0 RWS AO5 Allowable Opcode 5: See the description for bits 7:0
39 :32 0 RWS AO4 Allowable Opcode 4: See the description for bits 7:0
31 :24 0 RWS AO3 Allowable Opcode 3: See the description for bits 7:0
23 :16 0 RWS AO2 Allowable Opcode 2: See the description for bits 7:0
15 :08 0 RWS AO1 Allowable Opcode 1: See the description for bits 7:0
7 :00 05h RWS AO0
Allowable Opcode 0: Software programs an SPI opcode into this field
for use when initiating SPI commands through the Control Register.
Table 382. 60h: PBR0 - Protected BIOS Range #0
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
3080h at 4h
3083h at 4h
Memory Mapped IO BAR: RCBA Offset:
Bit Range Default Access Acronym Description
31 0 RW-Special WPE
Write Protection Enable: When set, this bit indicates that the Base and
Limit fields in this register are valid and that writes directed to addresses
between them (inclusive) must be blocked by hardware. The base and
limit fields are ignored when this bit is cleared.
30 :24 0 RV Reserved Reserved
23 :12 000h RW- Special PRL
Protected Range Limit: This field corresponds to SPI address bits
23:12 and specifies the upper limit of the protected range. Address bits
11:0 are assumed to be FFFh for the limit comparison. Any address
greater than the value programmed in this field is unaffected by this
protected range.
11 :00 000h RW- Special PRB
Protected Range Base: This field corresponds to SPI address bits 23:12
and specifies the lower base of the protected range. Address bits 11:0
are assumed to be 000h for the base comparison. Any address less than
the value programmed in this field is unaffected by this protected range.