Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
254
11.9.5.9 Offset 56h: OPTYPE – Opcode Type Configuration
This register is not writable when the SPI Configuration Lock-Down bit in Offset 00h:
SPIS – SPI Status register is set. Entries in this register correspond to the entries in the
Offset 58h: OPMENU – Opcode Menu Configuration register. Note that the definition
below only provides write protection for opcodes that have addresses associated with
them. Therefore, any erase or write opcodes that do not use an address should be
avoided (for example, “Chip Erase” and “Auto-Address Increment Byte Program”).
11.9.5.10 Offset 58h: OPMENU – Opcode Menu Configuration
This register is not writable when the SPI Configuration Lock-Down bit in Offset 00h:
SPIS – SPI Status register is set. Eight entries are available in this register to give BIOS
a sufficient set of commands for communicating with the flash device, while also
restricting what malicious software can do. This keeps the hardware flexible enough to
operate with a wide variety of SPI devices.
Table 379. 54h: PREOP - Prefix Opcode Configuration
Size: 16 bit Default: 0004h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
3074h
3075h
Memory Mapped IO BAR: RCBA Offset:
Bit Range Default Access Acronym Description
15 :08 0 RWS PO1
Prefix Opcode 1: Software programs an SPI opcode into this field that is
permitted to run as the first command in an atomic cycle sequence.
7 :00 04h RWS PO0
Prefix Opcode 0: Software programs an SPI opcode into this field that is
permitted to run as the first command in an atomic cycle sequence.
Table 380. 56h: OPTYPE - Opcode Type
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
3076h
3077h
Memory Mapped IO BAR: RCBA Offset:
Bit Range Default Access Acronym Description
15 :14 0 RWS OT7 Opcode Type 7: See the description for bits 1:0
13 :12 0 RWS OT6 Opcode Type 6: See the description for bits 1:0
11 :10 0 RWS OT5 Opcode Type 5: See the description for bits 1:0
9:08 0 RWS OT4 Opcode Type 4: See the description for bits 1:0
7:06 0 RWS OT3 Opcode Type 3: See the description for bits 1:0
5:04 0 RWS OT2 Opcode Type 2: See the description for bits 1:0
3:02 0 RWS OT1 Opcode Type 1: See the description for bits 1:0
1:00 0 RWS OT0
Opcode Type 0: This field specifies information about the corresponding
Opcode 0. This information allows the hardware to 1) know whether to
use the address field and 2) provide BIOS protection capabilities. The
hardware implementation also uses the read vs. write information for
modifying the behavior of the SPI interface logic. The encoding of the two
bits is:
00 = No Address associated with this Opcode and Read Cycle type
01 = No Address associated with this Opcode and Write Cycle type
10 = Address required; Read cycle type
11 = Address required; Write cycle type