Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
253
11.9.5.6 Offset 10h, 18h, 20h, 28h, 30h, 38h, 40h: SPID[0-6] – SPI Data N
11.9.5.7 Offset 50h: BBAR – BIOS Base Address
This register is not writable when the SPI Configuration Lock-Down bit in Offset 00h:
SPIS – SPI Status register is set.
11.9.5.8 Offset 54h: PREOP – Prefix Opcode Configuration
This register is not writable when the SPI Configuration Lock-Down bit in Offset 00h:
SPIS – SPI Status register is set.
Table 377. 10h, 18h, 20h, 28h, 30h, 38h, 40h: SPID[0-6] - SPI Data [0-6]
Size: 64 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
3030h at 4h
306Ch at 4h
Memory Mapped IO BAR: RCBA Offset:
Bit Range Default Access Acronym Description
63 :00 0 RW0 SCD
SPI Cycle Data N (SCD[N]): Similar definition as SPI Cycle Data 0.
However, this register does not begin shifting until SPID[N-1] has
completely shifted in/out.
Table 378. 50h: BBAR - BIOS Base Address
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
3070h
3073h
Memory Mapped IO BAR: RCBA Offset:
Bit Range Default Access Acronym Description
31 :24 0 RV RSVD Reserved
23 :08 0 RWS BSP
Bottom of System Flash: This field determines the bottom of the
System BIOS. The processor will not run programmed commands nor
memory reads whose address field is less than this value. This field
corresponds to bits 23:8 of the 3-byte address; bits 7:0 are assumed to
be 00h for this vector when comparing to a potential SPI address.
Software must always program 1’s into the upper, Don’t Care bits of this
field based on the flash size. Hardware does not know the size of the
flash array and relies upon the correct programming by software. The
default value of 0000h results in all cycles allowed.
Note: The SPI Host Controller prevents any Programmed cycle using the
Address Register with an address less than the value in this register.
Some flash devices specify that the Read ID command must have an
address of 0000h or 0001h. If this command must be supported with
these devices, it must be performed with the BBAR - BIOS Base Address
programmed to 0h. Some of these devices have actually been observed
to ignore the upper address bits of the Read ID command.
7 :00 0 RV RSVD Reserved