Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
252
11.9.5.4 Offset 04h: SPIA – SPI Address
11.9.5.5 Offset 08h: SPID0 – SPI Data 0
Table 375. 04h: SPIA - SPI Address
Size: 32 bit Default: 00XXXXXh Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
3024h
3027h
Memory Mapped IO BAR: RCBA Offset:
Bit Range Default Access Acronym Description
31 :24 0 RV RSVD Reserved
23 :00 0 RW SCA
SPI Cycle Address: This field is shifted out as the SPI Address (MSB
first).
Table 376. 08h: SPID0 - SPI Data 0
Size: 64 bit Default: XXXXXXXXh Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
3028h
302Bh
Memory Mapped IO BAR: RCBA Offset:
Bit Range Default Access Acronym Description
63 :00 0 RW0 SCD
SPI Cycle Data 0 (SCD0): This field is shifted out as the SPI Data on
the Master-Out Slave-In Data pin (SPI_MOSI) during the data portion of
the SPI cycle.
This register also shifts in the data from the Master-In Slave-Out pin
(SPI_MISO) into this register during the data portion of the SPI cycle.
The data is always shifted starting with the least significant byte, MSB to
LSB, followed by the next least significant byte, MSB to LSB, etc.
Specifically, the shift order on SPI in terms of bits within this register is:
7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-31…24-39...32…etc. Bit 56 is
the last bit shifted out/in. There are no alignment assumptions; byte 0
always represents the value specified by the cycle address.
Note that the data in this register may be modified by the hardware
during any programmed SPI transaction. Direct Memory Reads do not
modify the contents of this register. (This last requirement is needed in
order to properly handle the collision case described in
Section 11.9.5.13.)
This register is initialized to 0 by the reset assertion. However, the least
significant byte of this register is loaded with the first Status Register
read of the Atomic Cycle Sequence that the hardware automatically runs
out of reset. Therefore, bit 0 of this register can be read later to
determine if the platform encountered the boundary case in which the
SPI flash was busy with an internal instruction when the platform reset
deasserted.