Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
251
11.9.5.3 Offset 02h: SPIC – SPI Control
Table 374. 02h: SPIC - SPI Control
Size: 16 bit Default: 2005h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
3022h
3023h
Memory Mapped IO BAR: RCBA Offset:
Bit Range Default Access Acronym Description
15 0 RW SSMIE
SPI SMI# Enable: When set to 1, the SPI asserts an SMI# request
whenever the Cycle Done Status bit is 1.
14 1 RW DC
Data Cycle: When set to 1, there is data that corresponds to this
transaction. When 0, no data is delivered for this cycle, and the DBC and
data fields themselves are don’t cares.
13 :08 0 RW DBC
Data Byte Count: This field specifies the number of bytes to shift in or
out during the data portion of the SPI cycle. The valid settings (in
decimal) are any value from 0 to 63. The number of bytes transferred is
the value of this field plus 1.
Note that when this field is 00_0000b, then there is 1 byte to transfer
and that 11_1111b means there are 64 bytes to transfer.
7 0 RV RSVD Reserved
6:04 0 RW COP
Cycle Opcode Pointer: This field selects one of the programmed
opcodes in the Offset 58h: OPMENU – Opcode Menu Configuration to be
used as the SPI Command/Opcode. In the case of an Atomic Cycle
Sequence, this determines the second command.
30 RW SPOP
Sequence Prefix Opcode Pointer: This field selects one of the two
programmed prefix opcodes for use when performing an Atomic Cycle
Sequence. A value of 0 points to the opcode in the least significant byte
of the Offset 54h: PREOP – Prefix Opcode Configuration register. By
making this programmable, the processor supports flash devices that
have different opcodes for enabling writes to the data space vs. status
register.
21 RW ACS
Atomic Cycle Sequence: When set to 1 along with the SCGO assertion,
the processor will execute a sequence of commands on the SPI interface.
The sequence is composed of:
Atomic Sequence Prefix Command (8-bit opcode only)
Primary Command specified by software (can include address and data)
Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b.
The SPI Cycle in Progress bit remains set and the Cycle Done Status bit in
Offset 00h: SPIS – SPI Status register remains unset until the Busy bit in
the Flash Status Register returns 0.
10 RWS SCGO
SPI Cycle Go: This bit always returns 0 on reads. However, a write to
this register with a ‘1’ in this bit starts the SPI cycle defined by the other
bits of this register. The SPI Cycle in Progress (SCIP) bit in Offset 00h:
SPIS – SPI Status register gets set by this action. Hardware must ignore
writes to this bit while the SPI Cycle In Progress bit is set.
Hardware allows other bits in this register to be programmed for the
same transaction when writing this bit to 1. This saves an additional
memory write.
01 RSVDReserved