Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
250
11.9.5.2 Offset 00h: SPIS – SPI Status
Table 372. Bus 0, Device 31, Function 0, PCI Register Mapped Through RCBA BAR
Offset Start Offset End Register ID – Description Default
Value
3020h 3021h Offset 00h: SPIS - SPI Status 0001h
3022h 3023h Offset 02h: SPIC - SPI Control 2005h
3024h 3027h Offset 04h: SPIA - SPI Address 00XXXXXh
3028h 302Bh Offset 08h: SPID0 - SPI Data 0 XXXXXXXXh
3030h at 4h 306Ch at 4h Offset 10h, 18h, 20h, 28h, 30h, 38h, 40h: SPI[0-6] - SPI Data [0-6] 00000000h
3070h 3073h Offset 50h: BBAR - BIOS Base Address 00000000h
3074h 3075h Offset 54h: PREOP - Prefix Opcode Configuration 0004h
3076h 3077h Offset 56h: OPTYPE - Op Code Type 0000h
3078h 307Fh Offset 58h: OPMENU - OPCODE Menu Configuration 00000005h
3080h at 4h 3083h at 4h Offset 60h: PBR0 - Protected BIOS Range #0 00000000h
Table 373. 00h: SPIS - SPI Status
Size: 16 bit Default: 0001h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
3020h
3021h
Memory Mapped IO BAR: RCBA Offset:
Bit Range Default Access Acronym Description
15 0 RWL SCL
SPI Configuration Lock-Down: When set to 1, the SPI Static
Configuration information in offsets 50h through 6Bh can not be
overwritten. Once set to 1, this bit can only be cleared by a hardware
reset.
14 :4 0 RV RSVD Reserved
30 RWC BAS
Blocked Access Status: Hardware sets this bit to 1 when an access is
blocked from running on the SPI interface due to one of the protection
policies or when any of the programmed cycle registers are written while
a programmed access is already in progress. This bit is set for both
programmed accesses and direct memory reads that get blocked. This bit
remains asserted until cleared by software writing a 1 or hardware reset.
20 RWC CDS
Cycle Done Status: The processor sets this bit to 1 when the SPI Cycle
completes (i.e., SCIP bit is 0) after software sets the GO bit. This bit
remains asserted until cleared by software writing a 1 or hardware reset.
When this bit is set and the SPI bit in Offset 02h: SPIC – SPI Control is
set, an internal signal is asserted to the SMI# generation block. Software
must make sure this bit is cleared prior to enabling the SPI SMI#
assertion for a new programmed access.
This bit gets set after the Status Register Polling sequence completes
after reset deasserts. It is cleared before and during that sequence.
1 0 RV RSVD Reserved
01 RO SCIP
SPI Cycle In Progress: Hardware sets this bit when software sets the
SPI Cycle Go bit in the Offset 02h: SPIC – SPI Control. This bit remains
set until the cycle completes on the SPI interface. Hardware
automatically sets and clears this bit so that software can determine
when read data is valid and/or when it is safe to begin programming the
next command. Software must only program the next command when
this bit is 0.
This bit reports 1b during the Status Register Polling sequence after reset
deasserts; it is cleared when that sequence completes.