Datasheet

Introduction
Intel
®
Atom™ Processor E6xx Series Datasheet
25
1.2 Reference Documents
SCI System Control Interrupt. SCI is used in the ACPI protocol.
SDRAM Synchronous Dynamic Random Access Memory
SDVO
Serial Digital Video Out. SDVO is a digital display channel that serially transmits digital
display data to an external SDVO device. The SDVO device accepts this serialized format and
then translates the data into the appropriate display format (i.e., TMDS, LVDS, TV-Out).
SDVO Device
Third-party codec that uses SDVO as an input; may have a variety of output formats,
including DVI, LVDS, HDMI, TV-Out, etc.
SERR System Error. SERR is an indication that an unrecoverable error has occurred on an I/O bus.
SMC
System Management Controller or External Controller refers to a separate system
management controller that handles reset sequences, sleep state transitions, and other
system management tasks.
SMI
System Management Interrupt is used to indicate any of several system conditions (such as
thermal sensor events, throttling activated, access to System Management RAM, chassis
open, or other system state related activity).
TDMA Time Division Multiple Access
TEL Throttle Enforcement Limit
TCC
Thermal Control Circuit. A feature of the Intel
®
Atom™ Processor E6xx Series that is used to
cool the processor should its temperature exceed a predetermined activation temperature.
TMDS
Transition Minimized Differential Signaling. TMDS is a signaling interface from Silicon Image*
that is used in DVI and HDMI. TMDS is based on low-voltage differential signaling and
converts an 8-bit signal into a 10-bit transition minimized and DC-balanced signal (equal
number of 0s and 1s) in order to reduce EMI generation and improve reliability.
VCO Voltage Controlled Oscillator
Intel
®
VT
δ
Intel
®
Virtualization Technology
δ
Warm Reset Warm reset is when both RESET_B and PWROK are asserted.
Document Document Number / Location
Advanced Configuration and Power Interface,
Version 3.0 (ACPI)
http://www.acpi.info/spec.htm
IA-PC HPET (High Precision Event Timers)
Specification, Revision 1.0
http://www.intel.com/hardwaredesign/hpetspec_1.pdf
Intel
®
Atom™ Processor E6xx Series Specification
Update
http://download.intel.com/embedded/processor/specup
dt/324209.pdf
Intel
®
Atom™ Processor E6xx Series Thermal and
Mechanical Design Guidelines
http://download.intel.com/embedded/processor/designg
uide/324210.pdf
Low Pin Count Interface Specification, Revision 1.1
(LPC)
http://developer.intel.com/design/chipsets/industry/lpc.
htm
PCI Express* Base Specification, Rev. 1.0a http://www.pcisig.com/specifications
System Management Bus Specification, Version
1.0 (SMBus)
http://www.smbus.org/specs/
Notes:
1. Contact your Intel Field Representative for the latest version of this document.
Term Description