Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
249
Note:
1. Fast Read Protocol is not supported.
2. The Auto Address Increment type is not supported.
11.9.4.1.5 SPI Timings
The SPI interface is designed to fall within the following protocol timing specs. These
specs are intended to operate with most SPI Flash devices.
11.9.5 Host Side Interface
11.9.5.1 SPI Host Interface Registers
The SPI Host Interface are memory-mapped in the RCRB Chipset Memory Space in
range 3020h to 308Fh.
Warning: Address locations that are not listed are considered reserved register locations. Reads to
reserved registers may return non-zero values. Writes to reserved locations may cause
system failure.
The table below does NOT include the 3020h offset.
Write Enable 06 06 06 06
Page Write - 0A - -
Fast Read (1) 0B 0B 0B -
Ena Write Status - - - 50
256B Erase - DB - -
4 kByte Erase - - - 20
64 kB Erase D8 D8 D8 52
Chip Erase C7 - C7 60
Auto Add Inc (2) - - - AF
Power Down/Up B9 / AB B9 / AB B9 -
Read ID - 9F 90 AB or 90
Table 370. Instructions (Sheet 2 of 2)
Instruction ST* M25P80
(8 Mb)
ST* M45P80
(8 Mb)
NexFlash* NX25P SST* 25V040 (4 Mb)
SST* 25VF080 (8 Mb)
Table 371. SPI Cycle Timings
Parameter Minimum Value Description
SPI_CS# Setup 30 ns
SPI_CS# low to SPI_SCK high
SPI_CS# Hold 30 ns SPI_SCK low to SPI_CS# low
Clock High 20 ns Time that SPI_SCK is Driven high per clock period
Clock Low 30 ns Time that SPI_SCK is Driven Low per clock period