Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
247
11.9.4 SPI Protocol
Communication on the SPI bus is done with a Master – Slave protocol. Typical bus
topologies call for a single SPI Master with a single SPI Slave. The SPI interface consists of
a four wire interface: clock (CLK), master data out (Master Out Slave In (MOSI)), master
data in (Master In Slave Out (MISO)) and an active low chip select (CS#).
11.9.4.1 SPI Pin Level Protocol
SPI communicates utilizing a synchronous protocol with the clock driven by the Master.
After selecting a Slave by asserting the SPI_CS# signal, the Master generates eight
clock pulses per byte on the SPI_SCK wire, one clock pulse per data bit. Data flows from
master to slave on the SPI_MOSI wire and from slave to master on the SPI_MISO wire.
Data is setup and sampled on opposite edges of the SPI_SCK signal. Master drives data
off of the falling edge of the clock and slave samples on the rising edge of the clock.
Similarly, Slave drives data off of the falling edge of the clock. The master has more
flexibility on sampling schemes since it controls the clock.
Note: SPI_SCK flight times and the device SPI_MISO max valid times indicate that the rising
edge is not feasible for sampling the SPI_MISO input at the master for a 22 MHz clock
period with 50% duty cycle.
1. SPI supports 8- or 16-bit words, however all devices on the supported list only
operate on 8-bit words.
2. SPI specifies that data can be shifted MSB or LSB first, however all devices on the
supported list only operate MSB first.
Table 369. GPIO Boot Source Selection
GPIO[0] Description
1Boot from SPI
0Boot from LPC
Figure 9. Basic SPI Protocol