Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
246
11.8.5.2 Bus Time Out
If there is an error in the transaction, such that a device does not signal an
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. The processor will discard the cycle, and set HSTS.DE. The time out
minimum is 25 ms. The time-out counter inside the processor will start when the first
bit of data is transferred by the processor.
11.8.6 SMI#
The system can be set up to generate SMI# by setting HCTL.SE.
11.9 Serial Peripheral Interface
11.9.1 Overview
The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially
lower-cost alternative for system flash versus the Firmware Hub interface that is
available on the LPC pins.
11.9.2 Features
Goals for the SPI Architecture in the Product
• Support for Multiple SPI Flash Vendors
• Simple Hardware
— Equivalence to LPC-Based firmware hubs
— Provide write protection scheme
— Equivalent performance (boot time, resume time)
— Top swap functionality
— Support for E & F segments below 1 MB
— 64 kb-granular protection
— Max SPI flash size addressable by the processor is 8 MB (8 MB is hardware
allowed BIOS address decode range)
— Data throughput of the SPI bus is 20 Mbps
Note that the SPI does not provide support for very large BIOS sizes as easily as the
FWH interface. The processor SPI interface is restricted to one Chip Select pin. The
Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially lower-
cost alternative for system flash versus the Firmware Hub interface that is available on
the LPC pins.
11.9.3 External Interface
Table 368. SPI Pin Interface
Signal(s) Width Type IO Type Description
SPI_SCLK 1 O LVTTL, 3.3V Serial bit-rate clock 20/33 MHz
SPI_CS# 1 O LVTTL, 3.3V CS for slave
SPI_MOSI 1 O LVTTL, 3.3V Master data out / Slave In
SPI_MISO 1 I LVTTL, 3.3V Master data in / Slave out