Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
245
The host controller supports eight command protocols of the SMB interface (see the
System Management Bus Specification, Version 1.0.): Quick Command, Send Byte,
Receive Byte, Write Byte/Word, Read Byte/Word, Process call, Block Read, Block Write
and Block write-block read process call.
The host controller requires the various data and command fields be setup for the type
of command to be sent. When software sets HCTL.ST, the host controller will perform
the requested transaction and generate an SMI# (if enabled) when finished. Once
started, the values of the HCTL, HCMD, TSA, HD0, and HD1 should not be changed or
read until HSTS.BSY has been cleared. The host controller will update all registers while
completing the new command.
11.8.4 Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving SMBDATA
low to signal a start condition. When the processor releases SMBDATA, and samples it
low, then some other master is driving the bus and the processor must stop
transferring data. If the processor loses arbitration, it sets HSTS.BE, and if enabled,
generates an interrupt or SMI#. The CPU is responsible for restarting the transaction.
11.8.5 Bus Timings
The SMBus runs at between 10-100 kHz. The processor SMBus runs off of the backbone
clock.
The Min AC column indicates the minimum times required by the SMBus specification.
The processor tolerates these timings. When the processor is sending address,
command, or data bytes, it will drive data relative to the clock it is also driving. It will
not start toggling the clock until the start or stop condition meets proper setup and
hold. The processor will also guarantee minimum time between SMBus transactions as
a master.
11.8.5.1 Clock Stretching
Devices may stretch the low time of the clock. When the processor attempts to release
the clock (allowing the clock to go high), the clock will remain low for an extended
period of time. The processor monitors SMBCLK after it releases the bus to determine
whether to enable the counter for the high time of the clock. While the bus is still low,
the high time counter must not be enabled. The low period of the clock can be
stretched by an SMBus master if it is not ready to send or receive data.
Table 367. SMBus Timings
Timing Min AC Spec Name
t
LOW
4.7 µs Clock low period
t
HIGH
4.0 µs Clock high period
t
SU:DAT
250 ns Data setup to rising SMBCLK
t
HD:DAT
0 ns Data hold from falling SMBCLK
t
HD:STA
4.0 µs Repeat Start Condition generated from rising SMBCLK
t
SU:STA
4.7 µs First clock fall from start condition
t
SU:STO
4.0 µs Last clock rising edge to last data rising edge (stop condition)
t
BUF
4.7 µs Time between consecutive transactions