Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
243
11.8.2.3 Offset 02h: HCLK – Host Clock Divider
11.8.2.4 Offset 04h: TSA - Transmit Slave Address
This register contains the address of the intended target.
11.8.2.5 Offset 05h: HCMD - Host Command Register
This field is transmitted in the command field of the SMB protocol during the execution
of any command.
Table 361. 02h: HCLK – Host Clock Divider
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
02h
03h
Bit Range Default Access Acronym Description
15 :00 0 RW DIV
Divider: This controls how many legacy backbone clocks should be
counted for the generation of SMBCLK. Recommended values are listed
below:
SMBus
Frequency
Legacy Backbone
Frequency (33 MHz)
1 kHz 208Eh
10 kHz 0342h
50 kHz 00A7h
100 kHz 0054h
400 kHz 0015h
1 MHz 0009h
Table 362. 04h: TSA - Transmit Slave Address
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
04h
04h
Bit Range Default Access Acronym Description
07 :01 0 RW AD Address: 7-bit address of the targeted slave.
00 0 RW R Read: Direction of the host transfer. 1 = read, 0 = write
Table 363. 05h: HCMD - Command Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
05h
05h
Bit Range Default Access Acronym Description
07 :00 00h RW CMD Command: Command Field