Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
242
11.8.2.2 Offset 01h: HSTS - Host Status Register
02 :00 0 RW CMD
Command: Indicates the command the processor is to perform. If
enabled, the processor will generate an interrupt or SMI# when the
command has completed. If a reserved command is issued, the processor
will set HSTS.DE and perform no command, and will not operate until
HSTS.DE is cleared.
Table 360. 01h: HSTS - Host Status Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
01h
01h
Bit Range Default Access Acronym Description
07 :04 0 RO RSVD Reserved
03 0 RO BSY
Busy: When set, indicates the processor is running a command. No SMB
registers should be accessed while this bit is set.
02 0 RWC BE Bus Error: When set, indicates a transaction collision.
01 0 RWC DE
Device Error: When set, this indicates one of the following: Illegal
Command Field, an unclaimed cycle, or a time-out error.
00 0 RWC CS
Completion Status: When BSY is cleared, if this bit is set, the command
completed successfully. If cleared, the command did not complete
successfully.
Table 359. 00h: HCTL - Host Control Register (Sheet 2 of 2)
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
00h
00h
Bit Range Default Access Acronym Description
Bits Command Description
000 Quick: Uses TSA.
001
Byte: Uses TSA and CMD registers. TSA.R
determines the direction.
010
Byte Data: Uses TSA, CMD, and HD0 registers.
TSA.R determines the direction. If a read, HD0
will contain the read data.
011
Word Data: Uses TSA, CMD, HD0 and HD1
registers. TSA.R determines the direction. If a
read, HD0 and HD1 contain the read data.
100
Process Call: Uses TSA, HCMD, HD0 and HD1
registers. TSA.R determines the direction. Upon
completion, HD0 and HD1 contain the read data.
101
Block: Uses TSA, CMD, HD0 and HBD registers.
For writes, the count is stored in HD0 and
indicates how many bytes of data will be
transferred. For reads, the count is received and
stored in HD0. TSA.R determines the direction.
For writes, data is retrieved from the first n
(where n is equal to the specified count)
addresses of HBD. For reads, the data is stored
in HBD.
110 Reserved
111 Reserved