Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
241
11.8 SMBus Controller
11.8.1 Overview
The processor provides an SMBus 1.0-compliant host controller. The host controller
provides a mechanism for the CPU to initiate communications with SMB peripherals
(slaves).
11.8.2 I/O Registers
11.8.2.1 Offset 00h: HCTL - Host Control Register
Table 358. SMBus Controller Registers
Start End Symbol Register Name/Function
00 00 HCTL Host Control
01 01 HSTS Host Status
02 03 HCLK Host Clock Divider
04 04 TSA Transmit Slave Address
05 05 HCMD Host Command
06 06 HD0 Host Data 0
07 07 HD1 Host Data 1
20 3F HBD Host Block Data
Table 359. 00h: HCTL - Host Control Register (Sheet 1 of 2)
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
00h
00h
Bit Range Default Access Acronym Description
07 0 RW SE
SMI Enable: Enable generation of an SMI# upon completion of the
command.
06 0 RO RSVD Reserved
05 0 RW AE
Alert Enable: Software sets this bit to enable an interrupt/SMI# due to
SMBALERT#.
04 0 RW ST
Start/Stop: Initiates the command described in the CMD field. This bit
always reads zero. HSTS.BSY identifies when the processor has finished
the command.
03 0 RO RSVD Reserved