Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
240
11.7.2.7 Offset 38h: RGSMI – Resume Well GPIO SMI Enable
11.7.2.8 Offset 3Ch: RGTS – Resume Well GPIO Trigger Status
11.7.3 Theory of Operation
11.7.3.1 Power Wells
GPC0 – GPC4 are in the core well. GPR0 – GPR8 are in the resume well.
11.7.3.2 SMI# and SCI Routing
If GPE.EN[n] (whether in the core well [CGGPE] or resume well [RGGPE]) and
GPE0E.GPIO is set, and the GPIO is configured as an input, GPE0S.GPIO will be set. If
SMI.EN[n] (for both core well [CGSMI] and resume well [RGSMI]) and SMIE.GPIO is
set, and the GPIO is configured as an input, SMIS.GPIO will be set.
11.7.3.3 Triggering
A GPIO (whether in the core well or resume well) can cause an wake event and
SMI/SCI on either its rising edge, its falling edge, or both. These are controlled via the
CGTPE and CGTNE registers for the core well GPIOs, and RGTPE and RGTNE for the
resume well GPIOs. If the bit corresponding to the GPIO is set, the transition will cause
a wake event/SMI/SCI, and the corresponding bit in the trigger status register (CGTS
for core well GPIOs, RGTS for resume well GPIOs). The event can be cleared by writing
a ‘1’ to the status bit position.
Table 356. 38h: RGSMI – Resume Well GPIO SMI Enable
Size: 32 bit Default: 00000000h Power Well: Resume
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
38h
3Bh
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :09 0 RO RSVD Reserved
08 :00 00 RW EN
Enable: When set, when RGTS.TS[n] is set, the ACPI SMIS.GPIO bit will
be set.
Table 357. 3Ch: RGTS – Resume Well GPIO Trigger Status
Size: 32 bit Default: 00000000h Power Well: Resume
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
3Ch
3Fh
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :09 0 RO RSVD Reserved
08 :00 0 RWC TS
Trigger Status: When set, the corresponding GPIO, if enabled as input
via RGIO.IO[n], triggered an SMI#/SCI. This will be set if a ‘0’ to ‘1’
transition occurred and RGTPE.TE[n] was set, or a ‘1’ to ‘0’ transition
occurred and RGTNE.TE[n] was set. If both RGTPE.TE[n] and
RGTNE.TE[n] are set, then this bit will be set on both a ‘0’ to ‘1’ and a ‘1’
to ‘0’ transition.
This bit will not be set if the GPIO is configured as an output.