Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
239
11.7.2.4 Offset 2Ch: RGTPE – Resume Well GPIO Trigger Positive Edge Enable
11.7.2.5 Offset 30h: RGTNE – Resume Well GPIO Trigger Negative Edge Enable
11.7.2.6 Offset 34h: RGGPE – Resume Well GPIO GPE Enable
Table 353. 2Ch: RGTPE – Resume Well GPIO Trigger Positive Edge Enable
Size: 32 bit Default: 00000000h Power Well: Resume
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
2Ch
2Fh
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :09 0 RO RSVD Reserved
08 :00 0 RW TE
Trigger Enable: When set, the corresponding GPIO, if enabled as input
via RGIO.IO[n], will case an SMI#/SCI when a ‘0’ to ‘1’ transition occurs.
When cleared, the GPIO is not enabled to trigger an SMI#/SCI on a ‘0’ to
‘1’ transition. This bit has no meaning if GIO.IO[n] is cleared (i.e.
programmed for output)
Table 354. 30h: RGTNE – Resume Well GPIO Trigger Negative Edge Enable
Size: 32 bit Default: 00000000h Power Well: Resume
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
30h
33h
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :09 0 RO RSVD Reserved
08 :00 0 RW TE
Trigger Enable: When set, the corresponding GPIO, if enabled as input
via RGIO.IO[n], will case an SMI#/SCI when a ‘1’ to ‘0’ transition occurs.
When cleared, the GPIO is not enabled to trigger an SMI#/SCI on a ‘1’ to
‘0’ transition. This bit has no meaning if RGIO.IO[n] is cleared (i.e.
programmed for output)
Table 355. 34h: RGGPE – Resume Well GPIO GPE Enable
Size: 32 bit Default: 00000000h Power Well: Resume
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
34h
37h
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :09 0 RO RSVD Reserved
08 :00 00 RW EN
Enable: When set, when RGTS.TS[n] is set, the ACPI GPE0S.GPIO bit will
be set.