Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
238
11.7.2.2 Offset 24h: RGIO – Resume Well GPIO Input/Output Select
11.7.2.3 Offset 28h: RGLVL – Resume Well GPIO Level for Input or Output
08 :00 1FFh RW EN
Enable: When set, enables the pin as a GPIO. When cleared, the pin, if
muxed, returns to its normal use. This field has no effect on unmuxed
GPIOs.
Table 351. 24h: RGIO – Resume Well GPIO Input/Output Select
Size: 32 bit Default: 000001FFh Power Well: Resume
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
24h
27h
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :09 0 RO RSVD Reserved
08 :00 1FFh RW IO
Input/Output: When set, the GPIO signal (if enabled) is programmed
as an input. When cleared, the GPIO signal is programmed as an output.
If the pin is muxed, and not enabled, writes to these bits have no effect.
Table 352. 28h: RGLVL – Resume Well GPIO Level for Input or Output
Size: 32 bit Default: 00000000h Power Well: Resume
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
28h
2Bh
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :09 0 RO RSVD Reserved
08 :00 0 RW LVL
Level: If the GPIO is programmed to be an output (RGIO.IO[n] cleared),
then this bit is used by software to drive a value on the pin. 1 = high, 0 =
low. If the GPIO is programmed as an input, then this bit reflects the
state of the input signal (1 = high, 0 = low.) and writes will have no
effect.
The value of this bit has no meaning if the GPIO is disabled (RGEN.EN[n]
= ‘0’).
Table 350. 20h: RGEN – Resume Well GPIO Enable (Sheet 2 of 2)
Size: 32 bit Default: 000001FFh Power Well: Resume
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
20h
23h
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description