Datasheet
ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
237
11.7.1.8 Offset 1Ch: CGTS – Core Well GPIO Trigger Status
11.7.2 Resume Well GPIO I/O Registers
The control for the general purpose I/O signals is handled through an independent 64-
byte I/O space. The base offset for this space is selected by the GPIO_BAR register in
D31:F0 config space. The total GPIO in resume well is 9.
The format of these registers is the same as their core well counter parts (see
Section 11.7.1), the difference being these registers live in the resume well (which
range bit0 to bit8).
11.7.2.1 Offset 20h: RGEN – Resume Well GPIO Enable
Table 348. 1Ch: CGTS – Core Well GPIO Trigger Status
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
1Ch
1Fh
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :05 0 RO RSVD Reserved
04 :00 0 RWC TS
Trigger Status: When set, the corresponding GPIO, if enabled as input
via GIO.IO[n], triggered an SMI#/SCI. This will be set if a ‘0’ to ‘1’
transition occurred and GTPE.TE[n] was set, or a ‘1’ to ‘0’ transition
occurred and GTNE.TE[n] was set. If both GTPE.TE[n] and GTNE.TE[n]
are set, then this bit will be set on both a ‘0’ to ‘1’ and a ‘1’ to ‘0’
transition.
This bit will not be set if the GPIO is configured as an output.
Table 349. Resume Well GPIO Registers
Start End Name
20 23 RGEN – Resume Well GPIO Enable
24 27 RGIO – Resume Well GPIO Input/Output Select
28 2B RGLV – Resume Well GPIO Level for Input or Output
2C 2F RGTPE – Resume Well GPIO Trigger Positive Edge Enable
30 33 RGTNE – Resume Well GPIO Trigger Negative Edge Enable
34 37 RGGPE – Resume Well GPIO GPE Enable
38 3B RGSMI – Resume Well GPIO SMI Enable
3C 3F RGTS – Resume Well GPIO Trigger Status
Table 350. 20h: RGEN – Resume Well GPIO Enable (Sheet 1 of 2)
Size: 32 bit Default: 000001FFh Power Well: Resume
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
20h
23h
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :09 0 RO RSVD Reserved