Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
236
11.7.1.5 Offset 10h: CGTNE – Core Well GPIO Trigger Negative Edge Enable
11.7.1.6 Offset 14h: CGGPE – Core Well GPIO GPE Enable
11.7.1.7 Offset 18h: CGSMI – Core Well GPIO SMI Enable
Table 345. 10h: CGTNE – Core Well GPIO Trigger Negative Edge Enable
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
10h
13h
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :05 0 RO RSVD Reserved
04 :00 0 RW TE
Trigger Enable: When set, the corresponding GPIO, if enabled as input
via GIO.IO[n], will case an SMI#/SCI when a ‘1’ to ‘0’ transition occurs.
When cleared, the GPIO is not enabled to trigger an SMI#/SCI on a ‘1’ to
‘0’ transition. This bit has no meaning if GIO.IO[n] is cleared (i.e.
programmed for output)
Table 346. 14h: CGGPE – Core Well GPIO GPE Enable
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
14h
17h
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :05 0 RO RSVD Reserved
04 :00 00 RW EN
Enable: When set, when CGTS.TS[n] is set, the ACPI GPE0S.GPIO bit will
be set.
Table 347. 18h: CGSMI – Core Well GPIO SMI Enable
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
18h
1Bh
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :05 0 RO RSVD Reserved
04 :00 00 RW EN
Enable: When set, when CGTS.TS[n] is set, the ACPI SMIS.GPIO bit will
be set.