Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
235
11.7.1.2 Offset 04h: CGIO – Core Well GPIO Input/Output Select
11.7.1.3 Offset 08h: CGLVL – Core Well GPIO Level for Input or Output
11.7.1.4 Offset 0Ch: CGTPE – Core Well GPIO Trigger Positive Edge Enable
Table 342. 04h: CGIO – Core Well GPIO Input/Output Select
Size: 32 bit Default: 0000001Fh Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
04h
07h
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :05 0 RO RSVD Reserved
04 :00 1Fh RW IO
Input/Output: When set, the GPIO signal (if enabled) is programmed
as an input. When cleared, the GPIO signal is programmed as an output.
If the pin is muxed, and not enabled, writes to these bits have no effect.
Table 343. 08h: CGLVL – Core Well GPIO Level for Input or Output
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
08h
0Bh
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :05 0 RO RSVD Reserved
04 :00 0 RW LVL
Level: If the GPIO is programmed to be an output (GIO.IO[n] cleared),
then this bit is used by software to drive a value on the pin. 1 = high, 0 =
low. If the GPIO is programmed as an input, then this bit reflects the
state of the input signal (1 = high, 0 = low.) and writes will have no
effect.
The value of this bit has no meaning if the GPIO is disabled (GEN.EN[n] =
‘0’).
Table 344. 0Ch: CGTPE – Core Well GPIO Trigger Positive Edge Enable
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
0Ch
0Fh
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :05 0 RO RSVD Reserved
04 :00 0 RW TE
Trigger Enable: When set, the corresponding GPIO, if enabled as input
via GIO.IO[n], will case an SMI#/SCI when a ‘0’ to ‘1’ transition occurs.
When cleared, the GPIO is not enabled to trigger an SMI#/SCI on a ‘0’ to
‘1’ transition. This bit has no meaning if GIO.IO[n] is cleared (i.e.
programmed for output)