Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
234
11.7 General Purpose I/O
11.7.1 Core Well GPIO I/O Registers
The control for the general purpose I/O signals is handled through an independent 64-
byte I/O space. The base offset for this space is selected by the GPIO_BAR register in
D31:F0 config space.
Note: the Core Well GPIO registers are mapped to the “GPIO” pins and the resume well are
mapped to the GPIOSUS[n] pins.
If a bit is allocated for a GPIO that doesn’t exist, unless otherwise indicated, the bit will
always read as 0 and values written to that bit will have no effect.
All core well bits are reset by the standard conditions that assert RESET#, and all
suspend well bits are reset by the standard conditions that clear internal suspend
registers.
11.7.1.1 Offset 00h: CGEN – Core Well GPIO Enable
Table 340. GPIO I/O Register
Start End Name
00 03 CGEN – Core Well GPIO Enable
04 07 CGIO – Core Well GPIO Input/Output Select
08 0B CGLV – Core Well GPIO Level for Input or Output
0C 0F CGTPE – Core Well GPIO Trigger Positive Edge Enable
10 13 CGTNE – Core Well GPIO Trigger Negative Edge Enable
14 17 CGGPE – Core Well GPIO GPE Enable
18 1B CGSMI – Core Well GPIO SMI Enable
1C 1F CGTS – Core Well GPIO Trigger Status
Table 341. 00h: CGEN – Core Well GPIO Enable
Size: 32 bit Default: 0000001Fh Power Well: Core
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
00h
03h
Memory Mapped IO BAR: GPIO_BAR (IO) Offset:
Bit Range Default Access Acronym Description
31 :05 0 RO RSVD Reserved
04 :00 1Fh RW EN
Enable: When set, enables the pin as a GPIO. When cleared, the pin, if
muxed, returns to its normal use. This field has no effect on unmuxed
GPIOs. Bits 4:0 muxed between GPIO[4:0]