Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
233
11.6.3.4 Offset 0Dh: Register D - Flag Register (RTC Well)
11.6.4 Update Cycles
An update cycle occurs once a second, if B.SET bit is not asserted and the divide chain
is properly configured. During this procedure, the stored time and date will be
incremented, overflow will be checked, a matching alarm condition will be checked, and
the time and date will be rewritten to the RAM locations. The update cycle will start at
least 488μs after A.UIP is asserted, and the entire cycle will not take more than 1984μs
to complete. The time and date RAM locations (0-9) will be disconnected from the
external bus during this time.
11.6.5 Interrupts
The RTC interrupt is internally routed to interrupt 8, and is not it shared with any other
interrupt. IRQ8# from SERIRQ is ignored. The HPET can also be mapped to IRQ8#; in
this case, the RTC interrupt is blocked.
Table 338. 0Ch: Register C - Flag Register
Size: 8 bit Default: Power Well: RTC
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
0Ch
0Ch
Bit Range Default Access Acronym Description
07 0 RO IRQF
Interrupt Request Flag: This bit is an AND of the flag with its
corresponding interrupt enable in register B, and causes the RTC
Interrupt to be asserted.
06 0 RO PF Periodic Interrupt Flag: Set when the tap as specified by A.RS is one.
05 Undef RO AF Alarm Flag: Set after all Alarm values match the current time.
04 0 RO UF
Update-ended Flag: Set immediately following an update cycle for each
second.
03 :00 0 RO RSVD Reserved
Table 339. 0Dh: Register D - Flag Register (RTC Well)
Size: 8 bit Default: Power Well: RTC
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
0Dh
0Dh
Bit Range Default Access Acronym Description
07 1 RW VRT
Valid RAM and Time Bit: This bit should always be written as a 0 for
write cycle, however it will return a 1 for read cycles.
06 X RW RSVD
Reserved: This bit always returns a 0 and should be set to 0 for write
cycles.
05 :00 X RW DA
Date Alarm: These bits store the date of month alarm value. If set to
000000, then a don’t care state is assumed. If the date alarm is not
enabled, these bits will return zeros to mimic the functionality of the
Motorola 146818B. These bits are not affected by any reset assertion.