Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
232
11.6.3.2 Offset 0Bh: Register B - General Configuration
This register resides in the RTC well. Bits are reset by RSMRST#.
11.6.3.3 Offset 0Ch: Register C - Flag Register (RTC Well)
All bits in this register are cleared when this register is read. This register is cleared
upon RSMRST#.
03 :00 Undef RW RS
Rate Select: Selects one of 13 taps of the 15 stage divider chain. The
selected tap can generate a periodic interrupt if B.PIE bit is set.
Otherwise this tap will set C.PF.
Table 336. 0Ah: Register A (Sheet 2 of 2)
Size: 8 bit Default: Power Well: RTC
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
0Ah
0Ah
Bit Range Default Access Acronym Description
Bits Function Bits Function
0h Interrupt never toggles 8h 3.90625 ms
1h 3.90625 ms 9h 7.8125 ms
2h 7.8125 ms Ah 15.625 ms
3h 122.070 μs Bh 31.25 ms
4h 244.141 μs Ch 62.5 ms
5h 488.281 μs Dh 125 ms
6h 976.5625μs Eh 250 ms
7h 1.953125 ms Fh 500 ms
Table 337. 0Bh: Register B - General Configuration
Size: 8 bit Default: Power Well: RTC
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
0Bh
0Bh
Bit Range Default Access Acronym Description
07 Undef RW SET
Update Cycle Inhibit: When cleared, an update cycle occurs once each
second. If set, a current update cycle will abort and subsequent update
cycles will not occur until SET is returned to zero. When set, SW may
initialize time and calendar bytes safely.
06 0 RW PIE
Periodic Interrupt Enable: When set, and C.PF is set, an interrupt is
generated.
05 Undef RW AIE
Alarm Interrupt Enable: When set, and C.AF is set, an interrupt is
generated.
04 0 RW UIE
Update-ended Interrupt Enable: When set and C.UF is set, an
interrupt is generated.
03 0 RW SQWE Square Wave Enable: Not implemented.
02 Undef RW DM
Data Mode: When set, represents binary representation. When cleared,
denotes BCD.
01 Undef RW HF
Hour Format: When set, twenty-four hour mode is selected. When
cleared, twelve-hour mode is selected. In twelve hour mode, the seventh
bit represents AM (cleared) and PM (set).
00 Undef RW DSE Daylight Savings Enable: Not implemented