Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
231
11.6.3.1 Offset 0Ah: Register A
This register is in the RTC well, and is used for general configuration of the RTC
functions. None of the bits are affected by RSMRST# or any other reset signal.
Table 335. RTC Indexed Registers
Start End Name
00h 00h Seconds
01h 01h Seconds Alarm
02h 02h Minutes
03h 03h Minutes Alarm
04h 04h Hours
05h 05h Hours Alarm
06h 06h Day of Week
07h 07h Day of Month
08h 08h Month
09h 09h Year
0Ah 0Ah Register A
0Bh 0Bh Register B
0Ch 0Ch Register C
0Dh 0Dh Register D
0Eh 7Fh 114 Bytes of User RAM
Table 336. 0Ah: Register A (Sheet 1 of 2)
Size: 8 bit Default: Power Well: RTC
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
0Ah
0Ah
Bit Range Default Access Acronym Description
07 Undef RW UIP
Update in progress: When set, an update is in progress. When cleared,
the update cycle will not start for at least 488 µs. The time, calendar, and
alarm information in RAM is always available when this bit is cleared.
06 :04 Undef RW DV
Division Chain Select: Controls the divider chain for the oscillator, and
are not affected by RSMRST# or any other reset signal.
Bits Function Bits Function
0h Invalid 4h
Bypass 10 stages
(test mode only)
1h Invalid 5h
Bypass 15 stages
(test mode only)
2h Normal Operation 6h Divider Reset
3h
Bypass 5 stages
(test mode only)
7h Divider Reset