Datasheet
ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
227
11.4.4.5 Interrupt Delivery Data Value
11.4.5 PCI Express* Interrupts
When external devices through PCI Express* generate an interrupt, they will send the
message defined in the PCI Express* specification for generating INTA# - INTD#.
These will be translated internal assertions/de-assertions of INTA# - INTD#.
11.4.6 Routing of Internal Device Interrupts
The internal devices on the processor drive PCI interrupts. These interrupts can be
routed internally to any of PIRQA# - PIRQH#. This is done utilizing the “Device X
Interrupt Pin” and “Device X Interrupt Route” registers located in chipset configuration
space.
For each device, the “Device X Interrupt Pin” register exists which tells the functions
which interrupt to report in their PCI header space, in the “Interrupt Pin” register, for
the operating system. These registers are named D24IP, D23IP, D02IP, etc.
Additionally, the “Device X Interrupt Route” register tells the interrupt controller, in
conjunction with the “Device X Interrupt Pin” register, which of the internal PIRQA# -
PIRQH# to drive the devices interrupt onto. This requires the interrupt controller to
know which function each device is connected to.
11.5 Serial Interrupt
11.5.1 Overview
The interrupt controller supports a serial IRQ scheme. The signal used to transmit this
information is shared between the interrupt controller and all peripherals that support
serial interrupts. The signal line, SERIRQ, is synchronous to LPC clock, and follows the
sustained tristate protocol that is used by LPC signals. The serial IRQ protocol defines
this sustained tristate signaling in the following fashion:
• S - Sample Phase: Signal driven low
• R - Recovery Phase: Signal driven high
• T - Turn-around Phase: Signal released
The interrupt controller supports 21 serial interrupts. These represent the 15 ISA
interrupts (IRQ0- 1, 3-15), the four PCI interrupts, and the control signals SMI# and
IOCHK#. Serial interrupt information is transferred using three types of frames:
Table 331. Interrupt Delivery Data Value
Bit Description
31:16 0000h
15 Trigger Mode: RTE[x].TM
14
Delivery Status: 1 = Assert, 0 = Deassert. Only Assert messages are sent. This bit is always set to
‘1’.
13:12 00
11 Destination Mode: RTE[x].DSM
10:08 Delivery Mode: RTE[x].DLM
07:00 Vector: RTE[x].VCT