Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
226
11.4.3 Unsupported Modes
These delivery modes are not supported for the following reasons:
• NMI/INIT: This cannot be delivered while the CPU is in the Stop Grant state. In
addition, this is a break event for power management.
• SMI: There is no way to block the delivery of the SMI#, except through BIOS.
• Virtual Wire Mode B: The processor does not support the INTR of the 8259
routed to the I/OxAPIC pin 0.
11.4.4 Interrupt Delivery
11.4.4.1 Theory of Operation
Delivery of interrupts is done by writing to a fixed set of memory locations in CPU(s).
The following sequence is used:
• When the processor detects an interrupt event (active edge for edge-triggered
mode or a change for level-triggered mode), it sets or resets the internal IRR bit
associated with that interrupt.
• The processor delivers the message by performing a write cycle to the appropriate
address with the appropriate data. The address and data formats are described in
section below.
11.4.4.2 EOI
The data of the EOI message is the vector. This value is compared with all the vectors
inside the IOxAPIC, and any match causes RTE[x].RIRR to be cleared. The EOI is a
downstream 32-bit memory write cycle (with byte0 enabled) sent from CPU to
I/OxAPIC.
11.4.4.3 Interrupt Message Format
The processor writes the message to the backbone as a 32-bit memory write cycle. It
uses the following formats the Address and Data:
11.4.4.4 Interrupt Delivery Address Value
Table 330. Interrupt Delivery Address Value
Bit Description
31:20 FEEh
19:12 Destination ID: RTE[x].DID
11:04 Extended Destination ID: RTE[x].EDID
03
Redirection Hint: If RTE[x].DLM = “Lowest Priority” (001), this bit will be set. Otherwise, this bit
will be cleared.
02 Destination Mode: RTE[x].DSM
01:00 00