Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
224
11.4.2 Index Registers
The registers listed below can be accessed via the IDX register. When accessing these
registers, accesses must be done as DWs, otherwise unspecified behavior will result.
Software should not attempt to write to reserved registers. Some reserved registers
may return non-zero values when read.
11.4.2.1 Offset 00h: ID – Identification Register
11.4.2.2 Offset 01h: VS – Version Register
Table 326. Index Registers
Offset Symbol Register
00h ID Identification
01h VS Version
02-0Fh - Reserved
10-11h RTE0 Redirection Table 0
12-13h RTE1 Redirection Table 1
………
3E-3Fh RTE23 Redirection Table 23
40-FFh - Reserved
Table 327. 00h: ID – Identification Register
Size: 32 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
00h
00h
Bit Range Default Access Acronym Description
31 :28 0 RO RSVD Reserved
27 :24 0h RW AID
APIC Identification: Software must program this value before using
the APIC.
23 :16 0 RO RSVD Reserved
15 0 RW Scratchpad
14 0 RW RSVD Reserved. Writes to this bit have no effect.
13 :00 0 RO RSVD Reserved
Table 328. 01h: VS – Version Register (Sheet 1 of 2)
Size: 32 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
01h
01h
Bit Range Default Access Acronym Description
31 :24 0 RO RSVD Reserved
23 :16 17h RO MRE
Maximum Redirection Entries: This is the entry number (0 being the
lowest entry) of the highest entry in the redirection table. In the
processor this field is hardwired to 17h to indicate 24 interrupts.
15 0 RO PRQ
Pin Assertion Register Supported: The IOxAPIC does not implement
the Pin Assertion Register.