Datasheet

ACPI Devices

Intel

Atom™ Processor E6xx Series Datasheet

223

The Special Mask Mode enables all interrupts not masked by a bit set in the Mask

without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower

priority requests. In the Special Mask Mode, any interrupts may be selectively enabled

by loading the Mask Register with the appropriate pattern.

The special Mask Mode is set by OCW3.SSMM and OCW3.SMM set, and cleared when

OCW3.SSMM and OCW3.SMM are cleared.

11.3.9 Steering of PCI Interrupts

The processor can be programmed to allow PIRQ[A:H]# to be internally routed to

interrupts 3-7, 9-12, 14 or 15, through the PARC, PBRC, PCRC, PDRC, PERC, PFRC,

PGRC, and PHRC registers in the chipset configuration section. One or more PIRQx#

lines can be routed to the same IRQx input.

The PIRQx# lines are defined as active low, level sensitive. When PIRQx# is routed to

specified IRQ line, software must change the corresponding ELCR1 or ELCR2 register to

level sensitive mode. The processor will internally invert the PIRQx# line to send an

active high level to the 8259. When a PCI interrupt is routed onto the 8259, the

selected IRQ can no longer be used by an ISA device.

11.4 Advanced Peripheral Interrupt Controller (APIC)

11.4.1 Memory Registers

The APIC is accessed via an indirect addressing scheme. These registers are mapped

into memory space. The registers are shown below.

11.4.1.1 Address FEC00000h: IDX – Index Register

This 8-bit register selects which indirect register appears in the window register to be

manipulated by software. Software will program this register to select the desired APIC

internal register.

11.4.1.2 Address FEC00010h: WDW – Window Register

This 32-bit register specifies the data to be read or written to the register pointed to by

the IDX register. This register can be accessed only in DW quantities.

11.4.1.3 Address FEC00040h: EOI – EOI Register

When a write is issued to this register, the IOxAPIC will check the lower 8 bits written to

this register, and compare it with the vector field for each entry in the I/O Redirection

Table. When a match is found, RTE.RIRR for that entry will be cleared. If multiple

entries have the same vector, each of those entries will have RTE.RIRR cleared. Only