Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
222
11.3.6.6 Edge and Level Triggered Mode
In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge
for the entire controller. In the processor, this bit is disabled and a new register for
edge and level triggered mode selection, per interrupt input, is included. This is the
Edge/Level control Registers ELCR1 and ELCR2.
If an ELCR bit is ‘0’, an interrupt request will be recognized by a low to high transition
on the corresponding IRQ input. The IRQ input can remain high without generating
another interrupt. If an ELCR bit is ‘1’, an interrupt request will be recognized by a high
level on the corresponding IRQ input and there is no need for an edge detection. The
interrupt request must be removed before the EOI command is issued to prevent a
second interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until
after the falling edge of the first internal INTA#. If the IRQ input goes inactive before
this time, a default IRQ7 vector will be returned.
11.3.7 End Of Interrupt (EOI)
11.3.7.1 Normal EOI
In Normal EOI, software writes an EOI command before leaving the interrupt service
routine to mark the interrupt as completed. There are two forms of EOI commands:
Specific and Non- Specific. When a Non-Specific EOI command is issued, the 8259 will
clear the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode
of operation of the 8259 within the processor, as the interrupt being serviced currently
is the interrupt entered with the interrupt acknowledge. When the 8259 is operated in
modes which preserve the fully nested structure, software can determine which ISR bit
to clear by issuing a Specific EOI.
An ISR bit that is masked will not be cleared by a Non-Specific EOI if the 8259 is in the
Special Mask Mode. An EOI command must be issued for both the master and slave
controller.
11.3.7.2 Automatic EOI
In this mode, the 8259 will automatically perform a Non-Specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this
mode should be used only when a nested multi-level interrupt structure is not required
within a single 8259. The AEOI mode can only be used in the master controller.
11.3.8 Masking Interrupts
11.3.8.1 Masking on an Individual Interrupt Request
Each interrupt request can be masked individually by the Interrupt Mask Register
(IMR). This register is programmed through OCW1. Each bit in the IMR masks one
interrupt channel. Masking IRQ2 on the master controller will mask all requests for
service from the slave controller.
11.3.8.2 Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the
system priority structure during its execution under software control. For example, the
routine may wish to inhibit lower priority requests for a portion of its execution but
enable some of them for another portion.