Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
220
• Following initialization, an interrupt request (IRQ) input must make a low-to-high
transition to generate an interrupt.
• The Interrupt Mask Register is cleared.
• IRQ7 input is assigned priority 7.
• The slave mode address is set to 7.
• Special Mask Mode is cleared and Status Read is set to IRR.
11.3.4.2 ICW2
The second write in the sequence, ICW2, is programmed to provide bits [7:3] of the
interrupt vector that will be released during an interrupt acknowledge. A different base
is selected for each interrupt controller.
11.3.4.3 ICW3
The third write in the sequence, ICW3, has a different meaning for each controller.
• For the master controller, ICW3 is used to indicate which IRQ input line is used to
cascade the slave controller. Within the processor, IRQ2 is used. Therefore, bit 2 of
ICW3 on the master controller is set to a 1, and the other bits are set to 0’s.
• For the slave controller, ICW3 is the slave identification code used during an
interrupt acknowledge cycle. On interrupt acknowledge cycles, the master
controller broadcasts a code to the slave controller if the cascaded interrupt won
arbitration on the master controller. The slave controller compares this
identification code to the value stored in its ICW3, and if it matches, the slave
controller assumes responsibility for broadcasting the interrupt vector.
11.3.4.4 ICW4
The final write in the sequence, ICW4, must be programmed in both controllers. At the
very least, bit 0 must be set to a 1 to indicate that the controllers are operating in an
Intel
®
architecture-based system.
11.3.5 Operation Command Words (OCW)
These command words reprogram the Interrupt Controller to operate in various
interrupt modes.
• OCW1 masks and unmasks interrupt lines.
• OCW2 controls the rotation of interrupt priorities when in rotating priority mode,
and controls the EOI function.
• OCW3 is sets up ISR/IRR reads, enables/disables the Special Mask Mode SMM, and
enables/ disables polled interrupt mode.
11.3.6 Modes of Operation
11.3.6.1 Fully Nested Mode
In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being
the highest. When an interrupt is acknowledged, the highest priority request is
determined and its vector placed on the bus. Additionally, the ISR for the interrupt is
set. This ISR bit remains set until: the CPU issues an EOI command immediately before
returning from the service routine; or if in AEOI mode, on the trailing edge of the
second INTA#. While the ISR bit is set, all further interrupts of the same or lower
priority are inhibited, while higher levels will generate another interrupt.