Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
219
11.3.3.3 Hardware/Software Interrupt Sequence
1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or
seen high in level mode, setting the corresponding IRR bit.
2. The 8259 sends INTR active (high) to the CPU if an asserted interrupt is not
masked.
3. The CPU acknowledges the INTR and responds with an interrupt acknowledge
cycle.
4. Upon observing the special cycle, 8259 converts it into the two cycles that the
internal 8259 pair can respond to. Each cycle appears as an interrupt acknowledge
pulse on the internal INTA# pin of the cascaded interrupt controllers.
5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR
bit is set and the corresponding IRR bit is reset. On the trailing edge of the first
pulse, a slave identification code is broadcast internally by the master 8259 to the
slave 8259. The slave controller uses these bits to determine if it must respond
with an interrupt vector during the second INTA# pulse.
6. Upon receiving the second internally generated INTA# pulse, the 8259 returns the
interrupt vector. If no interrupt request is present, the 8259 will return vector 7
from the master controller.
7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of
the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate
EOI command is issued at the end of the interrupt subroutine.
11.3.4 Initialization Command Words (ICW)
Before operation can begin, each 8259 must be initialized. In the Intel
®
Atom™
Processor E6xx Series, this is a four byte sequence to ICW1, ICW2, ICW3, and ICW4.
The address for each 8259 initialization command word is a fixed location in the I/O
memory space: 20h for the master controller, and A0h for the slave controller.
11.3.4.1 ICW1
A write to the master or slave controller base address with data bit 4 equal to 1 is
interpreted as a write to ICW1. Upon sensing this write, 8259 expects three more byte
writes to 21h for the master controller, or A1h for the slave controller to complete the
ICW sequence.
A write to ICW1 starts the initialization sequence during which the following
automatically occur:
Table 324. Content of Interrupt Vector Byte
Master, Slave Interrupt Bits [7:3] Bits [2:0]
IRQ7,15
ICW2[7:3]
111
IRQ6,14 110
IRQ5,13 101
IRQ4,12 100
IRQ3,11 011
IRQ2,10 010
IRQ1,9 001
IRQ0,8 000