Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
218
11.3.2.9 Offset 4D1h: ELCR2 – Slave Edge/Level Control
11.3.3 Interrupt Handling
11.3.3.1 Generating
The 8259 interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each
interrupt level. These bits are used to determine the interrupt vector returned, and
status of any other pending interrupts. These bits are defined as follows:
• Interrupt Request Register (IRR): Set on a low to high transition of the
interrupt line in edge mode, and by an active high level in level mode.
• Interrupt Service Register (ISR): Set, and the corresponding IRR bit cleared,
when an interrupt acknowledge cycle is seen, and the vector returned is for that
interrupt.
• Interrupt Mask Register (IMR): Determines whether an interrupt is masked.
Masked interrupts will not generate INTR.
11.3.3.2 Acknowledging
The CPU generates an interrupt acknowledge cycle which is translated into an Interrupt
Acknowledge Special Cycle. The 8259 translates this cycle into two internal INTA#
pulses expected by the 8259 cores. The 8259 uses the first internal INTA# pulse to
freeze the state of the interrupts for priority resolution. On the second INTA# pulse, the
master or slave will sends the interrupt vector to the processor with the acknowledged
interrupt code. This code is based upon bits [7:3] of the corresponding ICW2 register,
combined with three bits representing the interrupt within that controller.
Table 323. 4D1h: ELCR2 – Slave Edge/Level Control
Size: 8 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
4D1h
Bit Range Default Access Acronym Description
07 :06 0 RW ECL[15:14]
Edge Level Control: In edge mode, (bit cleared), the interrupt is
recognized by a low to high transition. In level mode (bit set), the
interrupt is recognized by a high level. Bit 7 applies to IRQ15, and bit 6 to
IRQ14.
05 0 RO RSVD Reserved. The FERR# (IRQ13), cannot be programmed for level mode.
04 :01 0 RW ECL[12:9]
Edge Level Control: In edge mode, (bit cleared), the interrupt is
recognized by a low to high transition. In level mode (bit set), the
interrupt is recognized by a high level. Bit 4 applies to IRQ12, bit 3 to
IRQ11, bit 2 to IRQ10, and bit 1 to IRQ9.
00 0 RO RSVD
Reserved. The Real Time Clock (IRQ8#) cannot be programmed for level
mode.