Datasheet
ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
217
Offset 20h, A0h: OCW3 – Operational Control Word 3
11.3.2.8 Offset 4D0h: ELCR1 – Master Edge/Level Control
Table 321. 20h, A0h: OCW3 – Operational Control Word 3
Size: 8 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
20h, A0h
Bit Range Default Access Acronym Description
07 X RO RSVD Reserved. Must be 0.
06 0 WO SMM
Special Mask Mode: If this bit is set, the Special Mask Mode can be
used by an interrupt service routine to dynamically alter the system
priority structure while the routine is executing, through selective
enabling/ disabling of the other channel’s mask bits. Bit 6, the ESMM bit,
must be set for this bit to have any meaning.
05 1 WO ESMM
Enable Special Mask Mode: When set, the SMM bit is enabled to set or
reset the Special Mask Mode. When cleared, the SMM bit becomes a
“don’t care”.
04 :03 X WO O3S OCW3 Select: When selecting OCW3, bits 4:3 = “01”
02 X WO PMC
Poll Mode Command: When cleared, poll command is not issued. When
set, the next I/O read to the interrupt controller is treated as an interrupt
acknowledge cycle. An encoded byte is driven onto the data bus,
representing the highest priority level requesting service.
01 :00 10 WO RRC
Register Read Command: These bits provide control for reading the
ISR and Interrupt IRR. When bit 1=0, bit 0 will not affect the register
read selection. Following ICW initialization, the default OCW3 port
address read will be “read IRR”. To retain the current selection (read ISR
or read IRR), always write a 0 to bit 1 when programming this register.
The selected register can be read repeatedly without reprogramming
OCW3. To select a new status register, OCW3 must be reprogrammed
prior to attempting the read.
00 No Action
01 No Action
10 Read IRQ Register
11 Read IS Register
Table 322. 4D0h: ELCR1 – Master Edge/Level Control
Size: 8 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
4D0h
Bit Range Default Access Acronym Description
07 :03 0 RW ECL[7:3]
Edge Level Control: In edge mode, (bit cleared), the interrupt is
recognized by a low to high transition. In level mode (bit set), the
interrupt is recognized by a high level.
02 :00 0 RO RSVD
Reserved. The cascade channel, IRQ2, heart beat timer (IRQ0), and
keyboard controller (IRQ1), cannot be put into level mode.