Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
216
11.3.2.6 Offset 21h, A1h: OCW1 – Operational Control Word 1 (Interrupt Mask)
11.3.2.7 Offset 20h, A0h: OCW2 – Operational Control Word 2
Following a part reset or ICW initialization, the controller enters the fully nested mode
of operation. Non-specific EOI without rotation is the default. Both rotation mode and
specific EOI mode are disabled following initialization.
Table 319. 21h, A1h: OCW1 – Operational Control Word 1 (Interrupt Mask)
Size: 8 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
21h, A1h
Bit Range Default Access Acronym Description
07 :00 00h RW IRM
Interrupt Request Mask: When a 1 is written to any bit in this register,
the corresponding IRQ line is masked. When a 0 is written to any bit in
this register, the corresponding IRQ mask bit is cleared, and interrupt
requests will again be accepted by the controller. Masking IRQ2 on the
master controller will also mask the interrupt requests from the slave
controller.
Table 320. 20h, A0h: OCW2 – Operational Control Word 2
Size: 8 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
20h, A0h
Bit Range Default Access Acronym Description
07 :05 001 WO
Rotate and EOI Codes: R, SL, EOI - These three bits control the Rotate
and End of Interrupt modes and combinations of the two.
000 - Rotate in Auto EOI Mode (Clear)
001 - Non-specific EOI command
010 - No Operation
011 - Specific EOI Command
100 - Rotate in Auto EOI Mode (Set)
101 - Rotate on Non-Specific EOI Command
110 - Set Priority Command
111 - Rotate on Specific EOI Command
†L0 - L2 Are Used
04 :03 Undef WO OCW2 Select: When selecting OCW2, bits 4:3 = “00”
02 :00 Undef WO L2, L1, L0
Interrupt Level Select: L2, L1, and L0 determine the interrupt level
acted upon when the SL bit is active. A simple binary code selects the
channel for the command to act upon. When the SL bit is inactive, these
bits do not have a defined function; programming L2, L1 and L0 to 0 is
sufficient in this case.
Bits Interrupt Level Bits Interrupt Level
000 IRQ0/8 100 IRQ4/12
001 IRQ1/9 101 IRQ5/13
010 IRQ2/10 110 IRQ6/14
011 IRQ3/11 111 IRQ7/15