Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
215
11.3.2.3 Offset 21h: MICW3 – Master Initialization Command Word 3
11.3.2.4 Offset A1h: SICW3 – Slave Initialization Command Word 3
11.3.2.5 Offset 21h, A1h: ICW4 – Initialization Command Word 4 Register
Table 316. 21h: MICW3 – Master Initialization Command Word 3
Size: 8 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
21h
Bit Range Default Access Acronym Description
07 :03 Undef WO These bits must be programmed to zero.
02 Undef WO CCC
Cascaded Controller Connection: This bit must always be
programmed to a 1 to indicate the slave controller for interrupts 8-15 is
cascaded on IRQ2.
01 :00 Undef WO These bits must be programmed to zero.
Table 317. A1h: SICW3 – Slave Initialization Command Word 3
Size: 8 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
A1h
Bit Range Default Access Acronym Description
07 :03 X WO RSVD Reserved. Must be 0.
02 :00 0 WO
Slave Identification Code: This field must be programmed to 02h to
match the code broadcast by the master controller during the INTA#
sequence.
Table 318. 21h, A1h: ICW4 – Initialization Command Word 4 Register
Size: 8 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
21h, A1h
Bit Range Default Access Acronym Description
07 :05 0 WO RSVD Reserved. Must be 0.
04 0 WO SFNM
Special Fully Nested Mode: Should normally be disabled by writing a 0
to this bit. If SFNM=1, the special fully nested mode is programmed.
03 0 WO BUF
Buffered Mode: Must be cleared for non-buffered mode. Writing ‘1’ will
result in undefined behavior.
02 0 WO MSBM
Master/Slave in Buffered Mode: Not used. Should always be
programmed to 0.
01 0 WO AEOI
Automatic End of Interrupt: This bit should normally be programmed
to 0. This is the normal end of interrupt. If this bit is 1, the automatic end
of interrupt mode is programmed.
00 1 WO MM
Microprocessor Mode: This bit must be written to 1 to indicate that the
controller is operating in an Intel
®
architecture-based system. Writing 0
will result in undefined behavior.