Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
214
11.3.2.2 Offset 21h, A1h: ICW2 – Initialization Command Word 2
ICW2 is used to initialize the interrupt controller with the five most significant bits of
the interrupt vector address. The value programmed for bits[7:3] is used by the CPU to
define the base address in the interrupt vector table for the interrupt routines
associated with each IRQ on the controller. Typical ISA ICW2 values are 08h for the
master controller and 70h for the slave controller.
03 Undef WO LTIM Edge/Level Bank Select: Disabled. Replaced by ELCR1 and ELCR2.
02 Undef WO Reserved, set to 0.
01 Undef WO SNGL
Single or Cascade: Must be programmed to a 0 to indicate two
controllers operating in cascade mode.
00 Undef WO IC4
wICW4 Write Required: This bit must be programmed to a 1 to
indicate that ICW4 needs to be programmed.
Table 314. 20h, A0h: ICW1 – Initialization Command Word 1 (Sheet 2 of 2)
Size: 8 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
20h, A0h
Bit Range Default Access Acronym Description
Table 315. 21h, A1h: ICW2 – Initialization Command Word 2
Size: 8 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
21h, A1h
Bit Range Default Access Acronym Description
07 :03 Undef WO
Interrupt Vector Base Address: Bits [7:3] define the base address in
the interrupt vector table for the interrupt routines associated with each
interrupt request level input.
02 :00 Undef WO
Interrupt Request Level: When writing ICW2, these bits should all be
0. During an interrupt acknowledge cycle, these bits are programmed by
the interrupt controller with the interrupt to be serviced. This is combined
with bits [7:3] to form the interrupt vector driven onto the data bus
during the second INTA# cycle. The code is a three bit binary code:
Code Master Interrupt Slave Interrupt
000 IRQ0 IRQ8
001 IRQ1 IRQ9
010 IRQ2 IRQ10
011 IRQ3 IRQ11
100 IRQ4 IRQ12
101 IRQ5 IRQ13
110 IRQ6 IRQ14
111 IRQ7 IRQ15