Datasheet
ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
213
11.3.2 I/O Registers
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ0 - 7), and at A0h and A1h for the slave controller (IRQ8 - 13). These registers
have multiple functions, depending upon the data written to them. Below is a
description of the different register possibilities for each address:
11.3.2.1 Offset 20h, A0h: ICW1 – Initialization Command Word 1
A write to Initialization Command Word 1 starts the interrupt controller initialization
sequence, during which the following occurs:
• The Interrupt Mask register is cleared.
• IRQ7 input is assigned priority 7.
• The slave mode address is set to 7.
• Special Mask Mode is cleared and Status Read is set to IRR.
Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to
complete the initialization sequence.
Table 313. 8259 I/O Register Mapping
Port Aliases Register Name/Function
20h
24h, 28h, 2Ch, 30h, 34h,
38h, 3Ch
Master 8259 ICW1 Init. Cmd Word 1 Register
Master 8259 OCW2 Op Ctrl Word 2 Register
Master 8259 OCW3 Op Ctrl Word 3 Register
21h
25h, 29h, 2Dh, 31h, 35h,
39h, 3Dh
Master 8259 ICW2 Init. Cmd Word 2 Register
Master 8259 ICW3 Init. Cmd Word 3 Register
Master 8259 ICW4 Init. Cmd Word 4 Register
Master 8259 OCW1 Op Ctrl Word 1 Register
A0h
A4h, A8h, ACh, B0h, B4h,
B8h, BCh
Slave 8259 ICW1 Init. Cmd Word 1 Register
Slave 8259 OCW2 Op Ctrl Word 2 Register
Slave 8259 OCW3 Op Ctrl Word 3 Register
A1h
A5h, A9h, ADh, B1h, B5h,
B9h, BDh
Slave 8259 ICW2 Init. Cmd Word 2 Register
Slave 8259 ICW3 Init. Cmd Word 3 Register
Slave 8259 ICW4 Init. Cmd Word 4 Register
Slave 8259 OCW1 Op Ctrl Word 1 Register
4D0h - Master 8259 Edge/Level Triggered Register
4D1h - Slave 8259 Edge/Level Triggered Register
Table 314. 20h, A0h: ICW1 – Initialization Command Word 1 (Sheet 1 of 2)
Size: 8 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
20h, A0h
Bit Range Default Access Acronym Description
07 :05 Undef WO
These bits are MCS-85 specific, and not needed. Should be programmed
to “000”
04 Undef WO
ICW/OCW select: This bit must be a 1 to select ICW1 and enable the
ICW2, ICW3, and ICW4 sequence.