Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
212
11.2.2.4 Mapping Option #2: Standard Option (GC.LRE cleared)
Each timer has its own routing control. The interrupts can be routed to various
interrupts in the I/O APIC. TnC.IRC indicates which interrupts are valid options for
routing. If a timer is set for edge-triggered mode, the timers should not be shared with
any other interrupts.
11.3 8259 Interrupt Controller
11.3.1 Overview
The ISA compatible interrupt controller (8259) incorporates the functionality of two
8259 interrupt controllers. The following table shows how the cores are connected:
The slave controller is cascaded onto the master controller through master controller
interrupt input 2. Interrupts can individually be programmed to be edge or level, except
for IRQ0, IRQ2, IRQ8#. Active-low interrupt sources, such as the PIRQ#s, are
internally inverted before being sent to the 8259. In the following descriptions of the
8259’s, the interrupt levels are in reference to the signals at the internal interface of
the 8259’s, after the required inversions have occurred. Therefore, the term “high”
indicates “active”, which means “low” on an originating PIRQ#.
Table 311. Master 8259 Input Mapping
8259 Input Connected Pin / Function
0 Internal Timer / Counter 0 output or Multimedia Timer #0
1 IRQ1 via SERIRQ
2 Slave Controller INTR output
3 IRQ3 via SERIRQ, PIRQx
4 IRQ4 via SERIRQ, PIRQx
5 IRQ5 via SERIRQ, PIRQx
6 IRQ6 via SERIRQ, PIRQx
7 IRQ7 via SERIRQ, PIRQx
Table 312. Slave 8259 Input Mapping
8259 Input Connected Pin / Function
0 Inverted IRQ8# from internal RTC or HPET
1 IRQ9 via SERIRQ, SCI, or PIRQx
2 IRQ10 via SERIRQ, SCI, or PIRQx
3 IRQ11 via SERIRQ, SCI, or PIRQx
4 IRQ12 via SERIRQ, SCI, or PIRQx
5PIRQx
6 IDEIRQ, SERIRQ, PIRQx
7PIRQx