Datasheet

Revision History
Intel
®
Atom™ Processor E6xx Series Datasheet
21
Revision History
Date Revision Description
April 2013 005
Updated Section 5.2, “Introduction” on page 53
Updated Table 96, “C4h: GVD.FD – Functional Disable” on page 99
Updated Table 104, “Offset 00h: ID – Identifiers” on page 103
Updated Section 11.10.1, “Overview” on page 263
Updated Section 11.10.4.2, “Register Unlocking Sequence” on page 270
Updated Table 363, “05h: HCMD - Command Register” on page 243
Updated Table 364, “06h: HD0 - Host Data 0” on page 244
Updated Table 365, “07h: HD1 - Host Data 1” on page 244
Updated Table 404, “DC Current Characteristics” on page 276
Updated Table 405, “Operating Condition Power Supply and Reference DC Characteristics” on
page 277
Updated Table 406, “Active Signal DC Characteristics” on page 278
July 2011 004
Updated Section 1.3.11, “General Purpose I/O (GPIO)” on page 29
Updated Table 2, “Intel® Atom™ Processor E6xx Series SKU for Different Segments” on page 30
Updated Table 11, “SPI Interface Signals” on page 36
Updated Table 15, “Miscellaneous Signals and Clocks” on page 39
Updated Table 16, “General Purpose I/O Signals” on page 42
Updated Table 18, “Power and Ground Signals” on page 43
Updated Table 34, “Intel® Atom™ Processor E6xx Series Clock Domains” on page 51
Updated Table 36, “Memory Map” on page 55
Updated Section 5.4.2.1, “PCI Config Space” on page 59
Updated Table 71, “DRAM Address Decoder” on page 73
Updated Table 79, “08h: GVD.RIDCC - Revision Identification and Class Code” on page 92
Updated Table 107, “Offset 08h: RID - Revision Identification” on page 104
Updated Table 108, “Offset 09h: CC - Class Codes” on page 104
Updated Table 126, “PCI Type 1 Bridge Header” on page 112
Updated Section 8.1.2.4, “SMI/SCI Generation” on page 112
Updated Table 131, “Offset 08h: RID — Revision Identification” on page 115
Updated Table 177, “Intel® High Definition Audiob PCI Configuration Registers” on page 140
Updated Table 182, “08h: RID – Revision Identification Register” on page 143
Updated Table 275, “LPC Interface PCI Register Address Map” on page 188
Updated Table 279, “Offset 08h: RID – Revision ID” on page 189
Updated Section 10.3.4, “GPE0BLK—GPE0_BLK Base Address Register” on page 192
Updated Section 11.9.4.1, “SPI Pin Level Protocol” on page 247
Updated Table 368, “SPI Pin Interface” on page 246
Updated Table 371, “SPI Cycle Timings” on page 249
Updated Table 401, “Absolute Maximum Ratings” on page 274
Updated Table 403, “Thermal Design Power” on page 276 - Table 406, “Active Signal DC
Characteristics” on page 278
January 2011 003
Updated Table 2, “Intel® Atom™ Processor E6xx Series SKU for Different Segments” on page 30
Updated Table 403, “Thermal Design Power” on page 276
Updated Table 405, “Operating Condition Power Supply and Reference DC Characteristics” on
page 277
Updated Table 406, “Active Signal DC Characteristics” on page 278
Added missing information to register tables in Chapter 7.0, “Graphics, Video, and Display,”
Chapter 11.0, “ACPI Devices.”