Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
209
11.2.1.6 Offset 108h, 128h, 148h: T[0-2]CV – Timer [0-2] Comparator Value
Reads to this register return the current value of the comparator. The default value for
each timer is all 1’s for the bits that are implemented. Timer 0 is 64-bits wide. Timers 1
and 2 are 32-bits wide.
07 0 RO RSVD Reserved
06 0 RO/RW TVS
Timer Value Set: This bit will return 0 when read. Writes will only have
an effect for Timer 0 if it is set to periodic mode. Writes will have no
effect for Timers 1 and 2.
05 0/1 RO TS
Timer Size: 1 = 64-bits, 0 = 32-bits. Set for timer 0. Cleared for timers
1 and 2.
04 0/1 RO PIC
Periodic Interrupt Capable: When set, hardware supports a periodic
mode for this timer’s interrupt. This bit is set for timer 0, and cleared for
timers 1 and 2.
03 0 RO/RW TYP
Timer Type: If PIC is set, this bit is read/write, and can be used to
enable the timer to generate a periodic interrupt. This bit is RW for timer
0, and RO for timers 1 and 2.
02 0 RW IE
Interrupt Enable: When set, enables the timer to cause an interrupt
when it times out. When cleared, the timer count and generates status
bits, but will not cause an interrupt.
01 0 RW IT
Timer Interrupt Type: When cleared, interrupt is edge triggered. When
set, interrupt is level triggered and will be held active until it is cleared by
writing ‘1’ to GIS.Tn. If another interrupt occurs before the interrupt is
cleared, the interrupt remains active.
00 0 RO RSVD Reserved
Table 308. 100h, 120h, 140h: T[0-2]C – Timer [0-2] Config and Capabilities (Sheet 2 of
2)
Size: 64 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
100h, 120h, 140h
107h, 127h, 147h
Bit Range Default Access Acronym Description