Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
208
11.2.1.3 Offset 020h: GIS – General Interrupt Status
11.2.1.4 Offset 0F0h: MCV – Main Counter Value
11.2.1.5 Offset 100h, 120h, 140h: T[0-2]C – Timer [0-2] Config and
Capabilities
Table 306. 020h: GIS – General Interrupt Status
Size: 64 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
020h
027h
Bit Range Default Access Acronym Description
63 :03 0 RO RSVD Reserved
02 0 RWC T2 Timer 2 Status: Same functionality as T0, for timer 2.
01 0 RWC T1 Timer 1 Status: Same functionality as T0, for timer 1.
00 0 RWC T0
Timer 0 Status: In edge triggered mode, this bit always reads as 0. In
level triggered mode, this bit is set when an interrupt is active.
Table 307. 0F0h: MCV – Main Counter Value
Size: 64 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
0F0h
0F7h
Bit Range Default Access Acronym Description
63 :00 0 RW CV
Counter Value: Reads return the current value of the counter. Writes
load the new value to the counter. Timers 1 and 2 return 0 for the upper
32-bits of this register.
Table 308. 100h, 120h, 140h: T[0-2]C – Timer [0-2] Config and Capabilities (Sheet 1 of
2)
Size: 64 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
100h, 120h, 140h
107h, 127h, 147h
Bit Range Default Access Acronym Description
63 :32
See
Desc
RO IRC
Interrupt Rout Capability: Indicates I/OxAPIC interrupts the timer can
use:
• Timer 0,1: 00f00000h. Indicates support for IRQ20, 21, 22, 23
• Timer 2: 00f00800h. Indicates support for IRQ11, 20, 21, 22, and 23
31 :16 0 RO RSVD Reserved
15 0 RO FID FSB Interrupt Delivery: Not supported
14 0 RO FE FSB Enable: Not supported, since FID is not supported.
13 :9 00h RW IR
Interrupt Rout: Indicates the routing for the interrupt to the IOxAPIC.
If the value is not supported by this particular timer, the value read back
will not match what is written. If GC.LRE is set, then Timers 0 and 1 have
a fixed routing, and this field has no effect.
08 0 RO/RW T32M
Timer 32-bit Mode: When set, this bit forces a 64-bit timer to behave
as a 32-bit timer. For timer 0, this bit will be read/write and default to 0.
For timers 1 and 2, this bit is read only ‘0’.