Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
207
11.2.1.1 Offset 000h: GCID – General Capabilities and ID
11.2.1.2 Offset 010h: GC – General Configuration
100 107 T0C Timer 0 Config and Capabilities
108 10F T0CV Timer 0 Comparator Value
120 127 T1C Timer 1 Config and Capabilities
128 12F T1CV Timer 1 Comparator Value
140 147 T2C Timer 2 Config and Capabilities
148 14F T2CV Timer 2 Comparator Value
Table 304. 000h: GCID – General Capabilities and ID
Size: 64 bit Default: Undefined Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
000h
007h
Bit Range Default Access Acronym Description
63 :32
0429B1
7Fh
RO CTP
Counter Tick Period: Indicates a period of 69.841279ns, (14.1318 MHz
clock period)
31 :16 8086h RO VID Vendor ID: Value of 8086h indicates Intel.
15 1 RO LRC Legacy Rout Capable: Indicates support for Legacy Interrupt Rout.
14 0 RO RSVD Reserved
13 1 RO CS
Counter Size: This bit is set to indicate that the main counter is 64 bits
wide.
12 :08 02h RO NT Number of Timers: Indicates that 3 timers are supported.
07 :00 01h RO RID
Revision ID: Indicates that revision 1.0 of the specification is
implemented.
Table 305. 010h: GC – General Configuration
Size: 64 bit Default: Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
010h
017h
Bit Range Default Access Acronym Description
63 :02 0 RO RSVD Reserved
01 0 RW LRE
Legacy Route Enable: When set, interrupts will be routed as follows:
Timer 0 will be routed to IRQ0 in 8259 or IRQ2 in the I/O APIC
Timer 1 will be routed to IRQ8 in 8259 and I/O APIC
Timer 2 will be routed as per the routing in T2C
When set, the TNC.IR will have no impact for timers 0 and 1.
00 0 RW EN
Overall Enable: When set, the timers can generate interrupts. When
cleared, the main counter will halt and no interrupts will be caused by
any timer. For level-triggered interrupts, if an interrupt is pending when
this bit is cleared, the GIS.Tx will not be cleared.
Table 303. HPET Registers (Sheet 2 of 2)
Start End Symbol Register