Datasheet

LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
199
10.6 Root Complex Register Block Configuration
10.6.1 RCBA—Root Complex Base Address Register
§ §
00 0b RW WP
Write Protect: When set, access to BIOS is enabled for both read and
write cycles. When cleared, only read cycles are permitted to BIOS.
When written from a 0 to a 1 and LE is also set, an SMI_B is
generated. This ensures that only SMM code can update BIOS.
Table 296. Offset F0h: RCBA – Root Complex Base Address
Size: 32 bit Default: 00000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
F0h
F3h
Bit Range Default Access Acronym Description
31 : 14 0h RW BA
Base Address: Base Address for the root complex register block
decode range. This address is aligned on a 16KB boundary.
13 : 01 0h RO RSVD Reserved
00 0 RW EN
Enable:
1 = Enables the range specified in BA to be claimed as the RCRB.
Table 295. Offset D8h: BC – BIOS Control (Sheet 2 of 2)
Size: 32 bit Default: 00000100h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
D8h
DBh
Bit Range Default Access Acronym Description