Datasheet
LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
198
10.5.3 BC—BIOS Control Register
27 1b RW ED8
D8-DF Enable: Enables decoding of BIOS range FFD80000h –
FFDFFFFFh and FF980000h – FF9FFFFFh.
0 = Disable,
1 = Enable
26 1b RW ED0
D0-D7 Enable: Enables decoding of BIOS range FFD00000h –
FFD7FFFFh and FF900000h – FF97FFFFh.
0 = Disable
1 = Enable
25 1b RW EC8
C8-CF Enable: Enables decoding of BIOS range FFC80000h –
FFCFFFFFh and FF880000h – FF8FFFFFh.
0 = Disable
1 = Enable
24 1b RW EC0
C0-C7 Enable: Enables decoding of BIOS range FFC00000h –
FFC7FFFFh and FF800000h – FF87FFFFh.
0 = Disable
1 = Enable
23 : 00
000000
h
RO RSVD Reserved
Table 295. Offset D8h: BC – BIOS Control (Sheet 1 of 2)
Size: 32 bit Default: 00000100h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
D8h
DBh
Bit Range Default Access Acronym Description
31 : 09 0h RO RSVD Reserved
08 1b RW PFE
Prefetch Enable:
0 = Disable.
1 = Enable BIOS prefetching. An access to BIOS causes a 64-byte
fetch of the line starting at that region. Subsequent accesses
within that region result in data being returned from the prefetch
buffer.
Note: The prefetch buffer is invalidated when this bit is cleared, or a
BIOS access occurs to a different line than what is currently in
the buffer.
07 : 03
000000
b
RO RSVD Reserved
02 0b RW CD Cache Disable: Enable caching in read buffer for direct memory read.
01 0b RWLO LE
Lock Enable: When set, setting the WP bit will cause SMIs. When
cleared, setting the WP bit will not cause SMIs. Once set, this bit can
only be cleared by a RESET_B.
0 = Setting the BIOSWE will not cause SMIs.
1 = Enables setting the BIOSWE bit to cause SMIs.
Once set, this bit can only be cleared by a RESET_B.
Table 294. Offset D4h: BDE – BIOS Decode Enable (Sheet 2 of 2)
Size: 32 bit Default: FF000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
D4h
D7h
Bit Range Default Access Acronym Description